Data Sheet

HMC1061LC5

Rev. B | Page 7 of 18

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

GNDA

GNDA

GNDA

INP

INN

GNDA

VEECLK1

VCCCLK1

VCCCLK2

CLK_SELECT

GNDA

OUTP

OUTN

GNDA

VCCOB

VEE

HMC1061

TOP VIEW

(Not to Scale)

1

3

4

2

5

6

7

8

17

18

19

20

21

22

23

24

NOTES

1. EXPOSED PAD. EXPOSED PAD MUST

BE CONNECTED TO VEE.

PACKAGE

BASE

VEE

Figure 2. Pin Configuration

Table 4. Pin Function Descriptions

Pin No.

Mnemonic

Description

1, 2, 3, 6,

19, 22

GNDA

Analog Ground. This ground and clock ground must be connected to the same dc potential, but they can be

radio frequency (RF) isolated from each other if desired. See Figure 3 for the interface schematic.

4

INP

Positive Differential Signal Input. This input is a dc-coupled, ground referenced input with a nominal common-

mode voltage level of 0 V. Input impedance = 50 Ω, full-scale differential voltage = 1 V p-p, and a maximum input

level = 10 dBm. See Figure 4 for the interface schematic.

5

INN

Negative Differential Signal Input. This input is a dc-coupled, ground referenced input with a nominal common-

mode voltage level = 0 V. Input impedance = 50 Ω, full-scale differential voltage = 1 V p-p, and maximum input

level = 10 dBm. See Figure 4 for the interface schematic.

7, 16

VEECLK1,

VEECLK2

Negative Clock Buffer VEE Supplies. Nominal voltage = −4.75 V (VEE + VEE CLK1+ VEE CLK2) Current = −357 mA

nominal. See Figure 5 for the interface schematic.

8, 17

VCCCLK1,

VCCCLK2

Positive Clock Buffer VCC Supplies. Nominal voltage = 2 V (VccCLK1 + VccCLK2). See Figure 5 for the interface

schematic.

9, 12, 15

GNDC

Clock Ground. Clock ground and analog ground must be connected to the same dc potential but they can be

RF isolated from each other. See Figure 6 for the interface schematic.

10, 11

CLKAN,

CLKAP

Differential Clock A Input (Negative and Positive). These pins provide the clock to first rank device. These pins

also provide a properly timed clock to the second rank device when CLK_SELECT = 0 V. These inputs are dc-

coupled, ground referenced inputs with nominal common mode level of 0 V. Input impedance = 50 Ω. First

rank track mode: differential clock positive. First rank hold mode: differential clock negative. Maximum input

level = 10 dBm. See Figure 7 for the interface schematic.

13, 14

CLKBN,

CLKBP

Differential Clock B Input (Negative And Positive). These pins provide the clock to the second rank device if

CLK_SELECT = −4.75 V. These pins are dc-coupled, ground referenced inputs with a nominal common-mode

voltage level of 0 V. Input impedance = 50 Ω. Terminated if unused. Second rank track mode: differential clock

negative. Second rank hold mode: differential clock positive. Maximum input level = 10 dBm. See Figure 7 for

the interface schematic.

18

CLK_SELECT

Clock Mode Select Terminal. Nominal 0 V for Internal Clock B mode, current = 230 µA (nominal). Nominal

−4.75 V for external clock B mode, current = −230 µA (nominal). See Figure 8 for the interface schematic.

20, 21

OUTP, OUTN

Differential Output (Positive And Negative). These outputs are dc-coupled, ground referenced outputs with a

nominal common-mode voltage level of 0 V. Output impedance = 50 Ω. Intended to be dc or ac coupled to 50 Ω

load impedance. See Figure 9 for the interface schematic.

23

VCCOB

Positive VCC Supply for the 50 Ω Output Buffer. Nominal voltage = 2 V, current = 74 mA (nominal). This pin can

be biased with 1 < VCCOB < 3 V to adjust the output common-mode voltage to an exact desired value

between −0.5 V and +0.5 V. Output common-mode voltage adjustment has a sensitivity of approximately

VOCM (V) ~ 0.5 (VCCOB − 2). See Figure 11 for the interface schematic.

24, 26, 28,

30, 32

VEE

Negative VEE Supply. Nominal voltage = −4.75 V (VEE + VEECLK1+ VEECLK2), current = −357 mA (nominal).

See Figure 10 for the interface schematic.