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FS6600 Scheda tecnica(PDF) 2 Page - NXP Semiconductors |
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FS6600 Scheda tecnica(HTML) 2 Page - NXP Semiconductors |
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2 / 166 page ![]() NXP Semiconductors FS6600 Fail-safe system basis chip with multiple SMPS and LDO 3 Simplified application diagram aaa-036664 VBAT FS6600 BUCK1 BUCK2 BUCK3 LDO1 SPI AMUX VPRE S32S2 WAKE Wake 1 Wake 2 Analog and digital monitoring BOOST (5.74 V) FAIL SAFE SAFE MACHINE GPIO - 3.3 V CORE - 0.8 V FLASH - 1.8 V FAST - 3.3 V LDO2 ADC_Ref - 5.0 V PGOOD, RSTB INTB ADC_in FS0B Figure 1. FS6600 superset device of the family 4 Ordering information Package Part number [1] Application target Name Description Version MC33FS6600 M0ES FS6600 superset covering FS6600 family of devices MC33FS6600 M1ES Domain controller MC33FS6600 M2ES Domain controller HVQFN56 HVQFN56, plastic, thermally enhanced, very thin quad flat package, no leads, step-cut wettable flank, 56 terminals; 0.5 mm nominal pitch, 8 mm x 8 mm x 0.85 mm body SOT684-23 Table 1. Ordering information [1] To order parts in tape and reel, add the R2 suffix to the part number. M0 parts are non-programmed OTP configurations. For a custom OTP configuration, contact your local NXP sales representative. 4.1 Main OTP flavors MC33FS6600M1ES MC33FS6600M2ES VPRE Output voltage 3.3 V 3.3 V Slope compensation 70 mV/µs 70 mV/µs Current limitation 120 mV 120 mV FS6600 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 3 — 17 July 2024 Document feedback 2 / 166 |
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