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FS6600 Scheda tecnica(PDF) 71 Page - NXP Semiconductors |
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FS6600 Scheda tecnica(HTML) 71 Page - NXP Semiconductors |
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71 / 166 page  NXP Semiconductors FS6600 Fail-safe system basis chip with multiple SMPS and LDO Address Register Bit Symbol Value Description VPRE phase (delay) selection 000 no delay 001 delay 1 010 delay 2 011 delay 3 100 delay 4 101 delay 5 110 delay 6 24 OTP_CFG_CLOCK_1 5 to 3 VPRE_ph[2:0] 111 delay 7 VBUCK1 phase (delay) selection 000 no delay 001 delay 1 010 delay 2 011 delay 3 100 delay 4 101 delay 5 110 delay 6 5 to 3 BUCK1_ph[2:0] 111 delay 7 VBOOST phase (delay) selection 000 no delay 001 delay 1 010 delay 2 011 delay 3 100 delay 4 101 delay 5 110 delay 6 25 OTP_CFG_CLOCK_2 2 to 0 VBST_ph[2:0] 111 delay 7 VBUCK3 phase (delay) selection 000 no delay 001 delay 1 010 delay 2 011 delay 3 100 delay 4 101 delay 5 110 delay 6 5 to 3 BUCK3_ph[2:0] 111 delay 7 VBUCK2 phase (delay) selection 000 no delay 001 delay 1 010 delay 2 011 delay 3 100 delay 4 101 delay 5 110 delay 6 26 OTP_CFG_CLOCK_3 2 to 0 BUCK2_ph[2:0] 111 delay 7 Table 75. Main OTP bit description...continued FS6600 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 3 — 17 July 2024 Document feedback 71 / 166 |
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