FS6600 datasheet(21/166 Pages) NXP

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NXP Semiconductors

FS6600

Fail-safe system basis chip with multiple SMPS and LDO

aaa-036671

ABIST2 fail prevent the release of FS0B pin

Possibility to go back to INIT_FS by SPI

and remove the failing regulator from ABIST2 list

LBIST fail prevent the release of FS0B pin

ABIST1 fail prevent the release of FS0B pin

Possibility to go back to STANDBY by SPI

and restart the device

RSTB release

LBIST_OK == 1

Yes

Write all INIT_FS registers

With Reg/Reg_NOT procedure

Assign Vregx to ABIST2

Configure SVS if needed

Close INIT_FS

with 1x good WD refresh

STANDBY

ABIST1_OK == 1

Yes

Wait Vregx pwr up

Launch ABIST2 by SPI

Wait 1.2 ms

Decrease FLT_ERR_CNT to `0'

with WD_ERR_LIMIT

good WD refresh

ABIST2_OK == 1

Yes

Release FS0B with

RELEASE_FS0B[23:8]=

NOT_WD_SEED[8:23]

Figure 9. Application flowchart

14.6.2 Debug flowchart

In Debug mode, the Debug pin is managed according to Section 14.4 "Power sequencing" description. The

watchdog window is fully opened, and the watchdog refresh is not required.

FS6600

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Product data sheet

Rev. 3 — 17 July 2024

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