ADIN1300BCPZ-R7 datasheet(29/96 Pages) AD

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Data Sheet

ADIN1300

HARDWARE CONFIGURATION PINS

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Rev. B | 29 of 96

The ADIN1300 can operate in unmanaged or managed applica-

tions. In unmanaged applications, the desired operation of the PHY

is configured from hardware configuration pins without any software

intervention. For unmanaged applications, do not configure the

PHY to enter software power-down after reset to ensure that

the PHY immediately attempts to bring up links as configured by

the PHY_CFG1 and PHY_CFG0 hardware configuration pins after

power is applied to the device.

In managed applications, software is available to configure the

PHY via the management interface (MDIO/MDC). In this case, it is

possible to configure the PHY to enter software power-down mode

after reset, such that the PHY can be configured before linking is

attempted.

Hardware configuration pins are pins shared with functional pins

and the voltage level on the pin is sensed and latched upon exiting

from a reset. Some hardware configuration pins are multilevel

sense, while others are two-level sense. For multilevel sense pins,

using two resistors, R_LO and R_HI (see Figure 28), four different

voltage levels can be sensed, as shown in Table 21. For two-level

sense pins, only a pull down or pull up are relevant and this is

implemented with a 10 kΩ pull-down resistor or a 10 kΩ pull-up

resistor, respectively. Note that LED_0 must be pulled up to the

AVDD_3P3 rail rather than VDDIO.

Figure 28. Hardware Configuration Pin Implementation

Note that the values listed in Table 21 assume no extra loading

from circuitry external to the ADIN1300. It is likely that some

configuration pins can be connected to a field-programmable gate

array (FPGA) input that can have its own internal pull-up/pull-down

resistor. This loads the resistor divider voltage. Assuming a pull-up

resistor >43 kΩ and a pull-down resistor >37 kΩ, replace the 10 kΩ

resistor used in MODE_1 and MODE_4 with a 2.5 kΩ resistor.

Table 21. Configuration Modes

Mode

R_LO

R_HI

Voltage Threshold

MODE_1

10 kΩ

Open

MODE_2

10 kΩ

56 kΩ

>0.1 × VDDIO1

MODE_3

56 kΩ

10 kΩ

>0.5 × VDDIO1

MODE_4

Open

10 kΩ

>0.9 × VDDIO1

1 Note that the supply rail for the LED_0 pin is AVDD_3P3 rather than VDDIO.

Therefore, pull up any pull-up on the LED_0 pin to AVDD_3P3.

Table 21 shows recommended resistor values for the multilevel

sense pins with the corresponding voltage threshold range required

for each mode. Table 22 shows the voltage ranges involved for

each mode vs. VDDIO voltage. The voltage levels shown were

chosen to steer clear of standard VIH/VIL voltage levels to avoid any

shoot-through currents (and unknown voltage levels) in the input

driver of disabled devices connected to the pins. VIH/VIL voltage

levels do have voltage and device dependencies. Therefore, it may

not always be possible to avoid such artifacts.

Table 22. Voltage Levels for Modes vs. VDDIO Voltage

VDDIO1 Mode

1.8 V (V)

2.5 V (V)

3.3 V (LED_0 = 3.3 V) (V)

MODE_1

<0.18

<0.25

<0.33

MODE_2

>0.18

>0.25

>0.33

MODE_3

>0.9

>1.25

>1.65

MODE_4

>1.62

>2.25

>2.97

1 Note that the supply rail for the LED_0 pin is AVDD_3P3 rather than VDDIO.

Therefore, pull up any pull-up on the LED_0 pin to AVDD_3P3.

The large resistor values recommended in Table 21 were chosen to

minimize power consumption from the resistor ladder. Smaller value

resistors can also be used, but the user must maintain the same

resistor ratios for the values used.

When arranging hardware strapping, review how the MAC interface

pins default (whether internal pull-ups or pull-downs exist) on devi-

ces connected to the ADIN1300 to ensure they are not conflicting

with desired strapping configuration.

HARDWARE CONFIGURATION PIN

FUNCTIONS

The following functions are configurable from the ADIN1300 hard-

ware pins (see Table 23 for pin details):

►

PHY address

►

Forced/advertised PHY speed

►

Software power-down mode after reset

►

Downspeed enable

►

Energy detect power-down mode

►

EEE enable

►

Auto MDIX

►

MAC interface selection (RGMII/RMII/MII)

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