ADIN1300BCPZ-R7 datasheet(90/96 Pages) AD

90 / 96 page

Data Sheet

ADIN1300

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Rev. B | 90 of 96

Table 128. Bit Descriptions for GE_RMII_CFG (Continued)

Bits

Bit Name

Description

Reset

Access

GE_RMII_EN

This bit selects the RMII MAC interface mode. Note that the default value of this register bit is

configurable via hardware configuration pins. This allows the default operation of the PHY to be

configured in unmanaged applications. As RMII mode requires a 50 MHz reference clock, the

RMII interface must be configured from the hardware configuration pins and not from software.

0x0

R/W

Subsystem PHY Base Configuration Register

Address: 0xFF26, Reset: 0x0C86, Name: GE_PHY_BASE_CFG

This subsystem register allows the enhanced link detection function of the PHY to be configured for 100BASE-TX and for 1000BASE-T, and

allows 1000BASE-T retrain to be configured. Each time a PHY core software reset is issued, the PHY resets its registers, including the

1000BASE-T retrain enable register bit (B_1000_RTRN_EN bit, Address 0x1E.0xA001, Bit 0) and the enhanced link detection 1000BASE-T

and 100BASE-TX enable register bits (within the FLD_EN register, Address 0x1E.0x8E27). The default value of the B_1000_RTRN_EN bit

is set via the 1000BASE-T retrain enable configuration bit (GE_RTRN_EN_CFG, within this register). The default value of the enhanced link de-

tection 1000BASE-T enable register bits (within the FLD_EN register) are set via the GE_FLD_1000_EN_CFG bit and GE_FLD_100_EN_CFG

bit within this register. If the value of any of these enable configuration bits are changed, the corresponding 1000BASE-T retrain enable register

bit and the enhanced link detection 1000BASE-T and 100BASE-TX enable register bits in the PHY only change after a PHY software reset.

Table 129. Bit Descriptions for GE_PHY_BASE_CFG

Bits

Bit Name

Description

Reset

Access

[15:13]

RESERVED

Reserved.

0x0

GE_RTRN_EN_CFG

When this bit is set, the IEEE Standard 802.3 1000BASE-T retrain functionality is enabled in the PHY.

0x0

R/W

GE_FLD_1000_EN_CFG

When this bit is set, the enhanced link detection functionality is enabled when the PHY establishes a

1000BASE-T link.

0x1

R/W

GE_FLD_100_EN_CFG

When this bit is set, the enhanced link detection functionality is enabled when the PHY establishes a

100BASE-TX link.

0x1

R/W

[9:5]

RESERVED

Reserved.

0x8

R/W

GE_MAN_MDI_FLIP_CFG

This bit allows the order of the PHY dimensions to be reversed to accommodate alternative board

layouts and simplify the routing with a different RJ-45 orientation.

1: Inverts the mapping of the MDI pins. The analog physical pair 0 is mapped to digital logical pair 3,

analog physical pair 1 to digital logical pair 2, analog physical pair 2 to digital logical pair 1 and analog

physical pair 3 to digital logical pair 0.

0: Default MDI mapping.

0x0

R/W

GE_PHY_SFT_PD_CFG

When this bit is set, the PHY enters software power-down on exit from reset.

0x0

R/W

[2:0]

RESERVED

Reserved.

0x6

R/W

Subsystem Gigabit Ethernet PHY Interface Control Register

Address: 0xFF27, Reset: 0x0002, Name: GE_PHY_IF_CFG

This register is used to configure the PHY Interface.

Table 130. Bit Descriptions for GE_PHY_IF_CFG

Bits

Bit Name

Description

Reset

Access

[15:5]

RESERVED

Reserved.

0x0

[4:2]

GE_FIFO_DPTH

This field allows the PHY FIFO depth to be configured. Setting a larger value allows longer (jumbo)

packets to be handled but increases latency.

In latency sensitive applications, this field must always be left at the default value of 0x0 because this

value provides the lowest latency.

0x0

R/W

[1:0]

RESERVED

Reserved.

0x2

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