ADIN1300BCPZ-R7 datasheet(23/96 Pages) AD

23 / 96 page

Data Sheet

ADIN1300

THEORY OF OPERATION

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Rev. B | 23 of 96

MDI INTERFACE

The MDI connects the ADIN1300 to the Ethernet network via a

transformer, as shown in Figure 25. In 1000BASE-T mode, transmit

and receive occur simultaneously on each of the MDI_ x_x pairs.

In 10BASE-Te and 100BASE-TX modes, MDI_0_x are used to

transmit when operating in MDI configuration and to receive when

operating in MDIX configuration. The opposite is true of MDI_1_x in

10BASE-Te mode and 100BASE-TX mode. For example, MDI_1_x

are used to receive when operating in MDI configuration and

to transmit when operating in MDIX configuration. If auto MDIX

is enabled, the ADIN1300 automatically determines if the MDI

or MDIX configuration must be used. Otherwise, it is forced to

the chosen MDI or MDIX configuration. In 10BASE-Te mode and

100BASE-TX mode, MDI_2_x and MDI_3_x are unused. The Flip

MDI Dimensions section shows the mapping of the transmitter and

receiver to the pins for the various modes across speeds.

Figure 25. Media Dependent Interface

Flip MDI Dimensions

The ADIN1300 supports flipping the PHY dimensions to accom-

modate and simplify routing to different RJ-45 pinout orienta-

tions. The flip feature is user programmable over the MDIO inter-

face by accessing the GE_MAN_MDI_FLIP_CFG (Bit 4) of the

GE_PHY_BASE_CFG register (see Table 129). The default setting

is normal MDI pin mapping as shown in Table 17 and Table 18.

Table 17. MDI/MDIX Pin Mapping

MDI Pins

MDI Pin Mapping1

MDIX Pin Mapping1

10BASE-Te/

100BASE-TX 1000BASE-T

10BASE-Te/

100BASE-TX 1000BASE-T

MDI_0_P/

MDI_0_N

Transmit ±

Transmit A±

Receive B±

Receive ±

Transmit B±

Receive A±

MDI_1_P/

MDI_1_N

Receive ±

Transmit B±

Receive A±

Transmit ±

Transmit A±

Receive B±

MDI_2_P/

MDI_2_N

Not applicable Transmit C±

Receive D±

Not applicable Transmit D±

Receive C±

MDI_3_P/

MDI_3_N

Not applicable Transmit D±

Receive C±

Not applicable Transmit C±

Receive D±

1 Refer to IEEE802.3 Clause 40.8 for MDI/MDIX connector pinout.

Table 18. MDI Pair Flip Pin Mapping

MDI Pins

MDI Normal Mode,

GE_MAN_MDI_FLIP_CFG = 01

MDI Pair Flip,

GE_MAN_MDI_FLIP_CFG = 11

10BASE-Te/

100BASE-TX

1000BASE-T

10BASE-Te/

100BASE-TX 1000BASE-T

MDI_0_P/

MDI_0_N

Transmit ±

Transmit A±

Receive B±

Not applicable Transmit D±

Receive C±

MDI_1_P/

MDI_1_N

Receive ±

Transmit B±

Receive A±

Not applicable Transmit C±

Receive D±

MDI_2_P/

MDI_2_N

Not applicable

Transmit C±

Receive D±

Receive ±

Transmit B±

Receive A±

MDI_3_P/

MDI_3_N

Not applicable

Transmit D±

Receive C±

Transmit ±

Transmit A±

Receive B±

1 Refer to IEEE802.3 Clause 40.8 for MDI connector pinout.

RESET OPERATION

The ADIN1300 supports a number of resets that include power‑on

reset, hardware reset, and multiple software reset types. All of

these put the ADIN1300, including the PHY core, in a known state.

Whenever the PHY core is reset, the MAC interface output pins

(output pins with respect to the ADIN1300) are driven to a known

idle state. All outputs except RXC/RX_CLK are driven low and

RXC/RX_CLK is driven high.

Power-On Reset

The ADIN1300 includes power monitoring circuitry to monitor all of

the supplies. At power-up, the ADIN1300 is held in hardware reset

until each of the supplies has crossed its minimum rising threshold

value.

Brown-out protection is provided by monitoring the supplies to

detect if one or more of the supplies drops below a minimum falling

threshold value and holding the device in hardware reset until the

power is valid again.

Table 19. Brown-Out Protection Threshold Values

Supply

Minimum Falling Threshold Value (V)

AVDD_3P3

2.35

VDDIO

1.35

DVDD_0P9

0.7

Hardware Reset

A hardware reset is initiated by the POR circuitry or by asserting

the RESET_N pin low. Bring the pin low for a minimum of 10 µs.

Deglitch circuitry is included on this pin to reject pulses shorter than

~1 µs.

A pull-up or pull-down of 1 kΩ is recommended on this pin. Depend-

ing on the requirements of the MAC interface , the host may need

to ensure that the PHY is out of hardware reset and ready to

establish a link on power up, or alternatively may need to control

when the PHY is brought out of hardware reset.

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