ADIN1300BCPZ-R7 datasheet(72/96 Pages) AD

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Data Sheet

ADIN1300

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Rev. B | 72 of 96

Table 73. Bit Descriptions for FC_EN (Continued)

Bits

Bit Name

Description

Reset

Access

FC_EN

When set, this bit enables the frame checker.

0x1

R/W

Frame Checker Interrupt Enable Register

Address: 0x9406, Reset: 0x0001, Name: FC_IRQ_EN

This register is used to enable the frame checker interrupt. An interrupt is generated when a receive error occurs. Enable the frame

checker/generator interrupt in the interrupt mask register. Set the FC_FG_IRQ_EN bit (IRQ_MASK register, Address 0x0018). The interrupt

status can be read via the FC_FG_IRQ_STAT bit (IRQ_STATUS register, Address 0x0019).

Table 74. Bit Descriptions for FC_IRQ_EN

Bits

Bit Name

Description

Reset

Access

[15:1]

RESERVED

Reserved.

0x0

FC_IRQ_EN

When set, this bit enables the frame checker interrupt.

0x1

R/W

Frame Checker Transmit Select Register

Address: 0x9407, Reset: 0x0000, Name: FC_TX_SEL

This register is used to select the transmit side or receive side for frames to be checked. If set, frames received on the MAC interface to be

transmitted are checked. The frame checker can be used to verify that correct data is received over the MAC interface and is also useful if

remote loopback is enabled (set the LB_REMOTE_EN bit the in PHY_CTRL_STATUS_1 register, Address 0x0013, Bit 9) because it can be

used to check the received data after it is looped back at the MAC interface.

Table 75. Bit Descriptions for FC_TX_SEL

Bits

Bit Name

Description

Reset

Access

[15:1]

RESERVED

Reserved.

0x0

FC_TX_SEL

When set, this bit indicates that the frame checker must check frames received to be transmitted by the PHY.

0x0

R/W

1: check frames from the MAC interface to be transmitted by the PHY.

0: check frames received by the PHY from the remote end.

Frame Checker Maximum Frame Size Register

Address: 0x9408, Reset: 0x05F2, Name: FC_MAX_FRM_SIZE

This register specifies the maximum frame size. Frames longer than this size are counted as oversized frames.

Table 76. Bit Descriptions for FC_MAX_FRM_SIZE

Bits

Bit Name

Description

Reset

Access

[15:0]

FC_MAX_FRM_SIZE

This bit field specifies the max frame size. Received frames that are longer than this are counted as

oversized frames. Note, this frame length excludes the preamble and start frame delimiter.

0x5F2

R/W

Frame Checker Count High Register

Address: 0x940A, Reset: 0x0000, Name: FC_FRM_CNT_H

This register is a latched copy of Bits[31:16] of the 32-bit receive frame counter register. When the receive error counter (RX_ERR_CNT

register, Address 0x0014) is read, the receive frame counter register is latched. A copy of the receive frame counter register is latched when

RX_ERR_CNT register is read so that the error count and receive frame count are synchronized.

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