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Motore di ricerca datesheet componenti elettronici |
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ADIN1300BCPZ-R7 Scheda tecnica(PDF) 64 Page - Analog Devices |
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ADIN1300BCPZ-R7 Scheda tecnica(HTML) 64 Page - Analog Devices |
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64 / 96 page  Data Sheet ADIN1300 REGISTER SUMMARY analog.com Rev. B | 64 of 96 Table 56. Bit Descriptions for PHY_STATUS_1 (Continued) Bits Bit Name Description Reset Access 100: speed resolved to 1000BASE-T half duplex. 011: speed resolved to 100BASE-TX full duplex. 010: speed resolved to 100BASE-TX half duplex. 001: speed resolved to 10BASE-T full duplex. 000: speed resolved to 10BASE-T half duplex. 6 LINK_STAT A 1 indicates that a link is up. 0x0 R 5 TX_EN_STAT A 1 indicates that transmit enable (TX_EN) is asserted. 0x0 R 4 RX_DV_STAT A 1 indicates that receive data valid (RX_DV) is asserted. 0x0 R 3 COL_STAT A 1 indicates that collision is asserted. 0x0 R 2 AUTONEG_SUP A 1 indicates that both the local and remote PHYs support autonegotiation. 0x0 R 1 LP_PAUSE_ADV A 1 indicates that the link partner has advertised pause. The link partner pause advertisement bit indicates that the link partner advertised support for pause operation on full duplex links. This bit provides the same information as LP_PAUSE_ABLE. 0x0 R 0 LP_APAUSE_ADV A 1 indicates that the link partner has advertised asymmetric pause. The link partner asymmetric pause advertisement bit indicates that the link partner advertised support for asymmetric pause operation on full duplex links. This bit provides the same information as LP_APAUSE_ABLE. 0x0 R LED Control 1 Register Address: 0x001B, Reset: 0x0001, Name: LED_CTRL_1 This register provides access to various PHY LED control register bits. Table 57. Bit Descriptions for LED_CTRL_1 Bits Bit Name Description Reset Access [15:11] RESERVED Reserved. 0x0 R/W 10 LED_A_EXT_CFG_EN Enable Extended Configuration Set for LED_0 Pin. Also see LED_CTRL_2 register, Address 0x001C, Bits[3:0]. 0x0 R/W 1: enable extended configuration set for LED_0 pin. 0: disable extended configuration set for LED_0 pin. [9:8] RESERVED Reserved. 0x0 R [7:4] LED_PAT_PAUSE_DUR Internal LED Pattern Pause Duration for LED_0. After the blink pattern is driven out to the LED_0 pin, the last bit is held for a duration specified by the LED pattern pause duration register field. This duration is the value of LED tick duration (for example, the time for each bit) multiplied by the value of the LED pattern pause duration register field. Also see the LED_PAT register field (LED_CTRL_3 register, Address 0x001D, Bits[7:0]) and the LED_PAT_TICK_DUR register field (LED_CTRL_3 register, Address 0x001D, Bits[13:8]). The default blink is a 0.5 sec on and 0.5 sec off pattern. 0x0 R/W [3:2] LED_PUL_STR_DUR_SEL This bit field selects the duration of the pulse stretching. 0x0 R/W 11: user-programmable. In this case, the duration of the pulse stretching is programmable by the LED_PUL_STR_DUR register (Address 0xBC00, Bits[5:0]). 10: 102 ms. 01: 64 ms. 00: 32 ms. 1 LED_OE_N LED Active Low Output Enable Register Bit. 0x0 R/W 1: disable LED outputs. 0: enable LED outputs. |
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