ADIN1300BCPZ-R7 datasheet(33/96 Pages) AD

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Data Sheet

ADIN1300

HARDWARE CONFIGURATION PINS

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Rev. B | 33 of 96

Forced/Advertised PHY Speed

As outlined in Table 25, it is possible to advertise all or a subset of

PHY speed capabilities, select preferred slave or master, set half

duplex or full duplex mode, and enable or disable autonegotiation.

Autonegotiation is enabled for the first 11 rows in Table 25, such

as in the case of advertised speeds modes. It is also possible to

configure forced speed modes where autonegotiation is disabled

and the speed is forced (Row 12 to Row 14 of Table 25).

Referring to Table 25, three of the PHY_CFG1 and PHY_CFG0

hardware configuration pin settings result in the same link speed

configuration (Row 1, Row 2, and Row 4). However, Row 1 also

enables three other functions, Row 2 does not enable any extra

functions, and in Row 4, the ADIN1300 is configured to enter

software power-down mode after reset. The enabling or disabling of

autonegotiation and advertised speed settings can also be set us-

ing the standard IEEE registers, MII_CONTROL (Address 0x0000),

AUTONEG_ADV (Address 0x0004), and MSTR_SLV_CONTROL

(Address 0x0009).

Software Power-Down After Reset

If the ADIN1300 is configured so that it does not enter software

power-down mode after reset, the ADIN1300 attempts to bring up

links at the configured speeds and MDI/MDIX configuration after it

exits reset. If the ADIN1300 is configured so that it enters software

power-down mode after reset (Row 4), the ADIN1300 waits in

software power-down until it is configured over the MDIO interface,

at which point the PHY configuration can be set to exit software

power-down by software. The ADIN1300 can also be put into soft-

ware power-down mode by setting the SFT_PD bit (MII_CONTROL

Downspeed Configuration

If downspeed is enabled, the PHY down speeds to a lower speed

after a number of attempts if it cannot link at the highest speed

advertised. The use of downspeed requires autonegotiation to be

enabled with multiple speeds advertised. The default operation

of downspeed can be overwritten in software by writing to DN_

SPEED_TO_100_EN (PHY_CTRL_2 register, Address 0x0016,

Bit 11), DN_SPEED_TO_10_EN (PHY_CTRL_2 register, Address

0x0016, Bit 10), and NUM_SPEED_RETRY (PHY_CTRL_3 regis-

ter, Address 0x0017, Bits[12:10]).

Energy Detect Power-Down Configuration

If energy detect power-down is enabled and no energy is detected

at the MDI pins, the ADIN1300 enters a low power mode. There-

fore, this mode saves power where there is no cable connected or

the remote PHY is powered down.

Energy Efficient Ethernet

If EEE is enabled and also advertised by the remote PHY, the

ADIN1300 can enter a low power mode (low power idle) when no

data is being transmitted by either end. See the EEE, Low Power

Idle Mode section for more details.

Auto MDIX Configuration

Auto MDIX configuration mode is shared with the GP_CLK pin and

can be configured according to Table 26. This pin does not have an

internal pull-up resistor, so external resistors must be used to set

the MDI/MDIX mode.

Table 26. Auto MDIX Configuration

Configuration

MDIX_MODE

Manual MDI

MODE_1

Manual MDIX

MODE_2

Auto MDIX, Prefer MDIX

MODE_3

Auto MDIX, Prefer MDI

MODE_4

If auto MDIX is enabled (MODE_3 or MODE_4), the ADIN1300

automatically determines if the MDI or MDIX configuration must be

used. Otherwise, the ADIN1300 is forced to the chosen MDI or

MDIX configuration.

If enabling auto MDIX, the ADIN1300 supports auto MDIX with a

preference for MDI or MDIX. This determines which MDI/ MDIX

setting is first in the autocrossover algorithm. To achieve a faster

MDI/MDIX resolution in some cases, set both PHYs to the same

preferred configuration (MDI or MDIX) when a crossover cable is

used, and to opposite preferred configurations if a straight-through

cable is used, which has the advantage of still being able to work

with a mismatch of wiring and optimize the time to resolve auto

MDIX.

The default operation of auto MDIX can be overwritten in software

by writing to the AUTO_MDI_EN bit (PHY_CTRL_1 register, Ad-

dress 0x0012) and the MAN_MDIX bit (PHY_CTRL_1 register,

Address 0x0012).

MAC Interface Selection

The MAC interface selection is shared with the RX_CTL/RX_DV/

CRS_DV pin and RXC/RX_CLK pin, and can be configured ac-

cording to Table 27. In RGMII mode, it is possible to enable a

2 ns internal delay on RXC only or on both RXC and TXC. The

RX_CTL/RX_DV/CRS_DV pin and RXC/RX_CLK pin have weak

internal pull-down resistors. Therefore, by default, the ADIN1300 is

configured in RGMII mode with a 2 ns delay on RXC and TXC.

External resistors must be used to select any of the remaining MAC

interface modes.

When arranging hardware strapping, review how the MAC interface

pins default (whether internal pull-ups or pull-downs exist) on devi-

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