Data Sheet

AD9912

I/O REGISTER DESCRIPTIONS

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Rev. G | 35 of 38

Register 0x01A8—FTW0 (Frequency Tuning Word) (Continued)

Table 26.

Bits

Bit Name

Description

[23:16]

FTW0

These registers contain the FTW (frequency tuning word) for the DDS. The FTW determines the ratio of the AD9912 output

frequency to its DAC system clock. Register 0x01A6 is the least significant byte of the FTW. Note that the power-up default

is defined by start-up Pin S1 to Pin S4. Updates to the FTW results in an instantaneous frequency jump but no phase

discontinuity.

Register 0x01A9—FTW0 (Frequency Tuning Word) (Continued)

Table 27.

Bits

Bit Name

Description

[31:24]

FTW0

These registers contain the FTW (frequency tuning word) for the DDS. The FTW determines the ratio of the AD9912 output

frequency to its DAC system clock. Register 0x01A6 is the least significant byte of the FTW. Note that the power-up default

is defined by start-up Pin S1 to Pin S4. Updates to the FTW results in an instantaneous frequency jump but no phase

discontinuity.

Register 0x01AA—FTW0 (Frequency Tuning Word) (Continued)

Table 28.

Bits

Bit Name

Description

[39:32]

FTW0

These registers contain the FTW (frequency tuning word) for the DDS. The FTW determines the ratio of the AD9912 output

frequency to its DAC system clock. Register 0x01A6 is the least significant byte of the FTW. Note that the power-up default

is defined by start-up Pin S1 to Pin S4. Updates to the FTW results in an instantaneous frequency jump but no phase

discontinuity.

Register 0x01AB—FTW0 (Frequency Tuning Word) (Continued)

Table 29.

Bits

Bit Name

Description

[47:40]

FTW0

These registers contain the FTW (frequency tuning word) for the DDS. The FTW determines the ratio of the AD9912 output

frequency to its DAC system clock. Register 0x01A6 is the least significant byte of the FTW. Note that the power-up default

is defined by start-up Pin S1 to Pin S4. Updates to the FTW results in an instantaneous frequency jump but no phase

discontinuity.

Register 0x01AC—Phase

Table 30.

Bits

Bit Name

Description

[7:0]

DDS phase word

Allows the user to vary the phase of the DDS output. See the Direct Digital Synthesizer (DDS) section. Register 0x01AC is

the least significant byte of the phase offset word (POW). Note that a momentary phase discontinuity may occur as the phase

passes through 45° intervals.

Register 0x01AD—Phase (Continued)

Table 31.

Bits

Bit Name

Description

[13:8]

DDS phase word

Allows the user to vary the phase of the DDS output. See the Direct Digital Synthesizer (DDS) section. Register 0x01AC is

the least significant byte of the phase offset word (POW). Note that a momentary phase discontinuity may occur as the phase

passes through 45° intervals.