AD9912ASLASHPCBZ datasheet(17/38 Pages) AD

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Data Sheet

AD9912

THEORY OF OPERATION

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Rev. G | 17 of 38

The relative phase of the sinusoid can be controlled numerically,

as well. This is accomplished using the phase offset function of the

DDS (a programmable 14-bit value (Δphase); see the I/O Register

Map section). The resulting phase offset, ΔΦ (radians), is given by

∆Φ=2π ∆pℎase214

(3)

DIGITAL-TO-ANALOG (DAC) OUTPUT

The output of the digital core of the DDS is a time series of

numbers representing a sinusoidal waveform. This series is trans-

lated to an analog signal by means of a digital-to-analog converter

(DAC).

The DAC outputs its signal to two pins driven by a balanced

current source architecture (see the DAC output diagram in Figure

41). The peak output current derives from a combination of two

factors. The first is a reference current (IDAC_REF) that is established

at the DAC_RSET pin, and the second is a scale factor that is

programmed into the I/O register map.

The value of IDAC_REF is set by connecting a resistor (RDAC_REF)

between the DAC_RSET pin and ground. The DAC_RSET pin

is internally connected to a virtual voltage reference of 1.2 V

nominal, so the reference current can be calculated by

IDAC_REF= 1.2RDAC_REF

(4)

Note that the recommended value of IDAC_REF is 120 μA, which

leads to a recommended value for RDAC_REF of 10 kΩ.

The scale factor consists of a 10-bit binary number (FSC) program-

med into the DAC full-scale current register in the I/O register map.

The full-scale DAC output current (IDAC_FS) is given by

IDAC_FS=IDAC_REF72+192FSC1024

(5)

Using the recommended value of RDAC_REF, the full-scale DAC

output current can be set with 10-bit granularity over a range of

approximately 8.6 mA to 31.7 mA. 20 mA is the default value.

Figure 41. DAC Output

RECONSTRUCTION FILTER

The origin of the output clock signal produced by the AD9912

is the combined DDS and DAC. The DAC output signal appears

as a sinusoid sampled at fS. The frequency of the sinusoid is

determined by the frequency tuning word (FTW) that appears at the

input to the DDS. The DAC output is typically passed through an

external reconstruction filter that serves to remove the artifacts of

the sampling process and other spurs outside the filter bandwidth.

If desired, the signal can then be brought back on-chip to be

converted to a square wave that is routed internally to the output

clock driver or the 2× DLL multiplier.

Figure 42. DAC Spectrum vs. Reconstruction Filter Response

Because the DAC constitutes a sampled system, its output must

be filtered so that the analog waveform accurately represents the

digital samples supplied to the DAC input. The unfiltered DAC out-

put contains the (typically) desired baseband signal, which extends

from dc to the Nyquist frequency (fS/2). It also contains images

of the baseband signal that theoretically extend to infinity. Notice

that the odd images (shown in Figure 42) are mirror images of the

baseband signal. Furthermore, the entire DAC output spectrum is

affected by a sin(x)/x response, which is caused by the sample-and-

hold nature of the DAC output signal.

For applications using the fundamental frequency of the DAC out-

put, the response of the reconstruction filter should preserve the

baseband signal (Image 0), while completely rejecting all other

images. However, a practical filter implementation typically exhibits

a relatively flat pass band that covers the desired output frequency

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