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Data Sheet

AD9912

THEORY OF OPERATION

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Rev. G | 18 of 38

plus 20%, rolls off as steeply as possible, and then maintains

significant (though not complete) rejection of the remaining images.

Depending on how close unwanted spurs are to the desired signal,

a third-, fifth-, or seventh-order elliptic low-pass filter is common.

Some applications operate off an image above the Nyquist frequen-

cy, and those applications use a band-pass filter instead of a

low-pass filter.

The design of the reconstruction filter has a significant impact on

the overall signal performance. Therefore, good filter design and

implementation techniques are important for obtaining the best

possible jitter results.

FDBK_IN INPUTS

The FDBK_IN pins serve as the input to the comparators and out-

put drivers of the AD9912. Typically, these pins are used to receive

the signal generated by the DDS after it has been band-limited by

the external reconstruction filter.

A diagram of the FDBK_IN input pins is provided in Figure 43,

which includes some of the internal components used to bias the

input circuitry. Note that the FDBK_IN input pins are internally

biased to a dc level of ~1 V. Care should be taken to ensure that

any external connections do not disturb the dc bias because this

may significantly degrade performance.

Figure 43. Differential FDBK_IN Inputs

SYSCLK INPUTS

Functional Description

An external time base connects to the AD9912 at the SYSCLK pins

to generate the internal high frequency system clock (fS).

The SYSCLK inputs can be operated in one of the following three

modes:

►

SYSCLK PLL bypassed

►

SYSCLK PLL enabled with input signal generated externally

►

Crystal resonator with SYSCLK PLL enabled

A functional diagram of the system clock generator is shown in

Figure 44.

The SYSCLK PLL multiplier path is enabled by a Logic 0 (default)

in the PD SYSCLK PLL bit (Register 0x0010, Bit 4) of the I/O

the SYSCLK input pins by one of two means, depending on the

logic level applied to the 1.8 V CMOS CLKMODESEL pin. When

CLKMODESEL = 0, a crystal can be connected directly across the

SYSCLK pins. When CLKMODESEL = 1, the maintaining amp is

disabled, and an external frequency source (such as an oscillator

or signal generator) can be connected directly to the SYSCLK input

pins. Note that CLKMODESEL = 1 does not disable the system

clock PLL.

The maintaining amp on the AD9912 SYSCLK pins is intended for

25 MHz, 3.2 mm × 2.5 mm AT cut fundamental mode crystals with

a maximum motional resistance of 100 Ω. The following crystals,

listed in alphabetical order, meet these criteria (as of the revision

date of this data sheet):

►

AVX/Kyocera CX3225SB

►

ECS ECX-32

►

Epson/Toyocom TSX-3225

►

Fox FX3225BS

►

NDK NX3225SA

Note that although these crystals meet the preceding criteria ac-

cording to their data sheets, Analog Devices, Inc., does not guar-

antee their operation with the AD9912, nor does Analog Devices

endorse one supplier of crystals over another.

When the SYSCLK PLL multiplier path is disabled, the AD9912

must be driven by a high frequency signal source (250 MHz to 1

GHz). The signal thus applied to the SYSCLK input pins becomes

the internal DAC sampling clock (fS) after passing through an

internal buffer.

It is important to note that when bypassing the system clock PLL,

the LOOP_FILTER pin (Pin 31) should be pulled down to the analog

ground with a 1 kΩ resistor.

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