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AD9912A/PCBZ Scheda tecnica(PDF) 12 Page - Analog Devices |
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AD9912A/PCBZ Scheda tecnica(HTML) 12 Page - Analog Devices |
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12 / 38 page ![]() Data Sheet AD9912 TYPICAL PERFORMANCE CHARACTERISTICS analog.com Rev. G | 12 of 38 Figure 15. Absolute Phase Noise Using HSTL Driver, SYSCLK = 1 GHz Wenzel Oscillator (SYSCLK PLL Bypassed), HSTL Output Doubler Enabled Figure 16. Absolute Phase Noise Using CMOS Driver at 3.3 V, SYSCLK = 1 GHz Wenzel Oscillator (SYSCLK PLL Bypassed) DDS Run at 200 MSPS for 10 MHz Plot Figure 17. Absolute Phase Noise Using CMOS Driver at 1.8 V,SYSCLK = 1 GHz Wenzel Oscillator (SYSCLK PLL Bypassed) Figure 18. Power Dissipation vs. System Clock Frequency (SYSCLK PLL Bypassed), fOUT = fSYSCLK/5, HSTL Driver On, CMOS Driver On, SpurKiller Off Figure 19. Power Dissipation vs. Output Frequency SYSCLK = 1 GHz (SYSCLK PLL Bypassed), HSTL Driver On, CMOS Driver On, SpurKiller Off Figure 20. SFDR Comparison With and Without SpurKiller, SYSCLK = 1 GHz, fOUT = 400 MHz |
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