AD9912ASLASHPCBZ datasheet(5/38 Pages) AD

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Data Sheet

AD9912

SPECIFICATIONS

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Rev. G | 5 of 38

Table 2. (Continued)

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

SYSCLK PLL Enabled

VCO Frequency Range, Low Band

700

810

MHz

When in the range, use the low VCO band exclusively

VCO Frequency Range, Auto Band

810

900

MHz

When in the range, use the VCO auto band select

VCO Frequency Range, High Band

900

1000

MHz

When in the range, use the high VCO band exclusively

Maximum Input Rate of System Clock PFD

200

MHz

Without SYSCLK PLL Doubler

Input Frequency Range

200

MHz

Multiplication Range

Integer multiples of 2, maximum PFD rate and system clock frequency

must be met

Minimum Differential Input Level

632

mV p-p

Equivalent to 316 mV swing on each leg

With SYSCLK PLL Doubler

Input Frequency Range

100

MHz

Multiplication Range

132

Integer multiples of 8

Input Duty Cycle

Deviating from 50% duty cycle may adversely affect spurious

performance

Minimum Differential Input Level

632

mV p-p

Equivalent to 316 mV swing on each leg

Crystal Resonator with SYSCLK PLL Enabled

Crystal Resonator Frequency Range

MHz

AT cut, fundamental mode resonator

Maximum Crystal Motional Resistance

100

See the SYSCLK Inputs section for recommendations

CLOCK DRIVERS

HSTL Output Driver

Frequency Range

725

MHz

See Figure 27 for maximum toggle rate

Duty Cycle

Rise Time/Fall Time (20% to 80%)

115

165

100 Ω termination across OUT/OUTB, 2 pF load

Jitter (12 kHz to 20 MHz)

1.5

fOUT = 155.52 MHz, 50 MHz system clock input (see Figure 12 through

Figure 14 for test conditions)

HSTL Output Driver with 2× Multiplier

Frequency Range

400

725

MHz

Duty Cycle

Rise Time/Fall Time (20% to 80%)

115

165

100 Ω termination across OUT/OUTB, 2 pF load

Subharmonic Spur Level

−35

dBc

Without correction

Jitter (12 kHz to 20 MHz)

1.6

fOUT = 622.08 MHz, 50 MHz system clock input (see Figure 15 for test

conditions)

CMOS Output Driver (AVDD3/Pin 37) @ 3.3 V

Frequency Range

0.008

150

MHz

See Figure 29 for maximum toggle rate; the S-divider should be used

for low frequencies because the FDBK_IN minimum frequency is 10

MHz

Duty Cycle

With 20 pF load and up to 150 MHz

Rise Time/Fall Time (20% to 80%)

4.6

With 20 pF load

CMOS Output Driver (AVDD3/Pin 37) @ 1.8 V

Frequency Range

0.008

MHz

See Figure 28 for maximum toggle rate

Duty Cycle

With 20 pF load and up to 40 MHz

Rise Time/Fall Time (20% to 80%)

6.8

With 20 pF load

DAC OUTPUT CHARACTERISTICS

DCO Frequency Range (1st Nyquist Zone)

450

MHz

DAC lower limit is 0 Hz; however, the minimum slew rate for FDBK_IN

dictates the lower limit if using CMOS or HSTL outputs

Output Resistance

Single-ended (each pin internally terminated to AVSS)

Output Capacitance

Full-Scale Output Current

31.7

Range depends on DAC RSET resistor

Gain Error

−10

+10

% FS

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