AD9912ASLASHPCBZ datasheet(22/38 Pages) AD

22 / 38 page

Data Sheet

AD9912

THEORY OF OPERATION

analog.com

Rev. G | 22 of 38

MHz away from the fundamental. Therefore, when attempting to

reduce DAC spurs it is important to know the actual location of

the harmonic spur in the DAC output spectrum based on the DAC

sample rate so that its harmonic number can be reduced.

The mechanics of performing harmonic spur reduction is shown

in Figure 48. It essentially consists of two additional DDS cores

operating in parallel with the original DDS. This enables the user

to reduce two different harmonic spurs from the second to the 15th

with nine bits of phase offset control (±π) and eight bits of amplitude

control.

The dynamic range of the cancellation signal is further augmented

by a gain bit associated with each channel. When this bit is set,

the magnitude of the cancellation signal is doubled by employing

a 1-bit left-shift of the data. However, the shift operation reduces

the granularity of the cancellation signal magnitude. The full-scale

amplitude of a cancellation spur is approximately −60 dBc when the

gain bit is a Logic 0 and approximately −54 dBc when the gain bit is

a Logic 1.

The procedure for tuning the spur reduction is as follows:

1. Determine which offending harmonic spur to reduce and its

amplitude. Enter that harmonic number into Bit 0 to Bit 3 of

2. Turn off the fundamental by setting Bit 7 of Register 0x0013

and enable the SpurKiller channel by setting Bit 7 of Register

0x0500/Register 0x0505.

3. Adjust the amplitude of the SpurKiller channel so that it match-

es the amplitude of the offending spur.

4. Turn the fundamental on by clearing Bit 7 of Register 0x0013.

5. Adjust the phase of the SpurKiller channel so that maximum

interference is achieved.

Note that the SpurKiller setting is sensitive to the loading of the

DAC output pins, and that a DDS reset is required if a SpurKiller

channel is turned off. The DDS can be reset by setting Bit 0 of

The performance improvement offered by this technique varies

widely and depends on the conditions used. Given this extreme

variability, it is impossible to define a meaningful specification to

guarantee SpurKiller performance. Current data indicate that a 6 dB

to 8 dB improvement is possible for a given output frequency using

a common setting over process, temperature, and voltage. There

are frequencies, however, where a common setting can result in

much greater improvement. Manually adjusting the SpurKiller set-

tings on individual parts can result in more than 30 dB of spurious

performance improvement.

Figure 48. Spur Reduction Circuit Diagram

AD9912A/PCBZ Scheda tecnica(PDF) 22 Page - Analog Devices

AD9912A/PCBZ Scheda tecnica(HTML) 22 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38

Scheda tecnica Scarica

Link URL