Data Sheet

AD9912

SPECIFICATIONS

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Rev. G | 4 of 38

Table 1. (Continued)

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

Internally Generated DC Bias Voltage2

0.93

1.17

1.38

V

Differential Input Voltage Swing

632

mV p-p

Equivalent to 316 mV swing on each leg

Crystal Resonator with SYSCLK PLL Enabled

Motional Resistance

9

100

Ω

25 MHz, 3.2 mm × 2.5 mm AT cut

CLOCK OUTPUT DRIVERS

HSTL Output Driver

Differential Output Voltage Swing

1080

1280

1480

mV

Output driver static, see Figure 27 for output swing vs.

frequency

Common-Mode Output Voltage2

0.7

0.88

1.06

V

CMOS Output Driver

Output driver static, see Figure 28 and Figure 29 for

output swing vs. frequency

Output Voltage High (VOH)

2.7

V

IOH = 1 mA, Pin 37 = 3.3 V

Output Voltage Low (VOL)

0.4

V

IOL = 1 mA, Pin 37 = 3.3 V

Output Voltage High (VOH)

1.4

V

IOH = 1 mA, Pin 37 = 1.8 V

Output Voltage Low (VOL)

0.4

V

IOL = 1 mA, Pin 37 = 1.8 V

TOTAL POWER DISSIPATION

DDS Only

637

765

mW

Power-on default, except SYSCLK PLL by-passed and

CMOS driver off; SYSCLK = 1 GHz; HSTL driver off;

spur reduction off; fOUT = 200 MHz

DDS with Spur Reduction On

686

823

mW

Same as “DDS Only” case, except both spur reduction

channels on

DDS with HSTL Driver Enabled

657

788

mW

Same as “DDS Only” case, except HSTL driver enabled

DDS with CMOS Driver Enabled

729

875

mW

Same as “DDS Only” case, except CMOS driver and

S-divider enabled and at 3.3 V; CMOS fOUT = 50 MHz

(S-divider = 4)

DDS with HSTL and CMOS Drivers Enabled

747

897

mW

Same as “DDS Only” case, except both HSTL and

CMOS drivers enabled; S-divider enabled and set to 4;

CMOS fOUT = 50 MHz

DDS with SYSCLK PLL Enabled

648

777

mW

Same as “DDS Only” case, except 25 MHz on SYCLK

input and PLL multiplier = 40

Power-Down Mode

13

16

mW

Using either the power-down and enable register or the

PWRDOWN pin

1 Pin 14 is in the AVDD3 group, but it is recommended that Pin 14 be tied to Pin 1.

2 AVSS = 0 V.

AC SPECIFICATIONS

fS = 1 GHz, DAC RSET = 10 kΩ, unless otherwise noted. Power supply pins within the range specified in the DC Specifications section.

Table 2.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

FDBK_IN INPUT

Pin 40, Pin 41

Input Frequency Range

10

400

MHz

Minimum Differential Input Level

225

mV p-p

−12 dBm into 50 Ω; must be ac-coupled

40

V/μs

SYSTEM CLOCK INPUT

Pin 27, Pin 28

SYSCLK PLL Bypassed

Input Frequency Range

250

1000

MHz

Maximum fOUT is 0.4 × fSYSCLK

Duty Cycle

45

55

%

Minimum Differential Input Level

632

mV p-p

Equivalent to 316 mV swing on each leg