AD9858SLASHFDPCB datasheet(26/32 Pages) AD

26 / 32 page

AD9858

Rev. C | Page 26 of 32

Profile Selection

A profile consists of a specific group of memory registers (see

Table 6). In the AD9858, each profile contains a 32-bit frequency

tuning word and a 14-bit phase offset word. Each profile is

selectable via two external profile select pins (PS0 and PS1), as

defined in Table 12. The specific mapping of registers to profiles is

detailed in the Register Bit Descriptions section. The user should

be aware that selection of a profile is internally synchronized

with DDS CLK using the SYNCLK timing. That is, SYNCLK is

used to synchronize the assertion of the profile select pins (PS0

and PS1). Therefore, the PS0 and PS1 pins must be set up and

held around the rising edge of SYNCLK.

Table 12.

PS1

PS0

Profile

The profiles are available to the user to provide rapid changing

of device parameters via external hardware, which alleviates the

speed limitations imposed by the I/O port. For example, the user

might preprogram the four phase offset registers with values that

correspond to phase increments of 90°. By controlling the PS0 and

PS1 pins, the user can implement π/2 phase modulation. The data

modulation rate is much higher than that possible by repeatedly

reloading a single phase offset register via the I/O port.

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