AD9858SLASHFDPCB datasheet(21/32 Pages) AD

21 / 32 page

AD9858

Rev. C | Page 21 of 32

tRDHOZ

tRDLOV

tADV

tAHD

tADV

tAHD

tRDLOV

tRDHOZ

SPECIFICATION

15ns

5ns

15ns

10ns

VALUE

ADDRESS TO DATA VALID TIME (MAXIMUM)

ADDRESS HOLD TIME TO RD SIGNAL INACTIVE (MINIMUM)

RD LOW TO OUTPUT VALID (MAXIMUM)

RD HIGH TO DATA THREE-STATE (MAXIMUM)

DESCRIPTION

ADDR[5:0]

D[7:0]

Figure 36. I/O Port Read Cycle Timing (Parallel)

Serial Programming Mode

In serial programming mode, the I/O port uses a chip select pin

(CS), a serial clock pin (SCLK), an I/O reset pin (IORESET),

and either one or two serial data pins (SDIO and/or SDO). The

number of serial data pins used depends on the configuration of

the I/O port, that is, whether it has been configured for 2-wire

or 3-wire serial operation as defined by the control function

serial data pin. In 3-wire mode, the SDIO pin operates as a

serial data input pin only, and the SDO pin acts as the serial

output. The maximum rate of SCLK is guaranteed only for write

operation.

The serial port is an SPI-compatible serial interface. Serial port

communication occurs in two phases. Phase 1 is an instruction

cycle consisting of an 8-bit word. The MSB of the instruction

byte flags the ensuing operation as a read or write operation.

The six LSBs define the serial address of the target register as

defined in the register map. The instruction byte format is given in

Table 5.

D7 (MSB)

D0 (LSB)

1: Read

0: Write

Phase 2 of a serial port communication contains the data to be

routed to/from the addressed register. The number of bytes

transferred during Phase 2 depends on the length of the target

serial register address be transferred.

Both phases of a serial port communication require the serial

data clock (SCLK) to be operating. When writing to the device,

serial bits are transferred on the rising edge of SCLK. When

reading from the device, serial output bits are transferred on the

falling edge of SCLK. The bit order for both phases of a serial

port communication is selectable via the control function register.

The CS pin serves as a chip select control line. When CS is in a

Logic 1 state, the SDO and SDIO pins are disabled (forced into a

high impedance state). When the CS pin is in a Logic 0 state,

the SDO and SDIO pins are active. This allows multiple devices

to reside on a single serial bus. If multiple devices are connected

to the same serial bus, then communication with an individual

device is accomplished by setting CS to a Logic 0 state on the

target device, but to a Logic 1 state on all other devices. In this

way, serial communication occurs only between the controller

and the target device.

When I/O synchronization is lost between the AD9858 and

the external controller, the IORESET pin provides a means

to reestablish synchronization without initializing the entire

device. Asserting the active high IORESET pin resets the serial

port state machine. This terminates the current I/O operation

and puts the device into a state in which the next eight SCLK

pulses are expected to be the instruction byte of the next I/O

transfer. Any information previously written to the memory

registers during the last valid communication cycle prior to loss

of synchronization remains intact.

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