AD9858SLASHFDPCB datasheet(28/32 Pages) AD

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AD9858

Rev. C | Page 28 of 32

EVALUATION BOARDS

The AD9858 has three different evaluation board designs. The

first design is the traditional DDS evaluation board (see Figure 38).

In this design, the DDS is clocked and the output is taken

directly from the DAC. The analog mixer and PLL blocks are

made available for separate evaluation.

The second design is a fractional divide loop (see Figure 39).

This evaluation board was designed to incorporate the DDS, the

phase frequency detector, and the charge pump. In this

application, the DDS is used in a PLL loop. Unlike a fixed

divider used in traditional PLL loops, the output signal is

divided and fed back to the phase frequency detector by the

DDS. To do this, the output signal of the PLL loop is fed to the

DDS as REFCLK. The DDS is programmed to match the

reference input frequency. Because the DDS output frequency

can take on 232 potential values between 0 Hz and one-half of

the PLL loop output frequency, this enables frequency

resolution on the order of 470 MHz, assuming a PLL loop

output frequency of 2 GHz.

The third design is a translation loop or offset loop (see Figure 37).

In this design, the analog mixer is incorporated into the feedback

path of the loop. This allows direct up-conversion to the

transmission frequency.

The three evaluation boards have separate schematics, BOMs, and

instructions. See www.analog.com/dds for more information.

Table 13. Evaluation Boards for the AD9858

Model

Description

AD9858/PCBZ

AD9858 Frequency Synthesizer Board

AD9858/FDPCB

AD9858 Fractional Divide Loop Frequency

Synthesizer Board

AD9858/TLPCBZ

AD9858 Translation Loop Frequency

Synthesizer Board

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