AD9858SLASHFDPCB datasheet(20/32 Pages) AD

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AD9858

Rev. C | Page 20 of 32

I/O Port Functionality

The I/O port can operate in either serial or parallel programming

mode. Mode selection is accomplished via the SPSELECT pin.

The ability to read back the contents of a register is provided in

both modes to facilitate the debug process during the user’s

prototyping phase of a design. In either mode, however, the

reading back of profile registers requires that the profile select

pins (PS0 and PS1) be configured to select the desired register

bank. When reading a register that resides in one of the profiles,

the register address acts as an offset to select one of the registers

among the group of registers defined by the profile. The profile

select pins control the base address of the register bank and

select the appropriate register grouping.

Parallel Programming Mode

In parallel programming mode, the I/O port makes use of eight

bidirectional data pins (D7 to D0), six address input pins (ADDR5

to ADDR0), a read input pin (RD), and a write input pin (WR).

A register is selected by providing the proper address combination

as defined in the register map (see

). Read or write

functionality is invoked by pulsing the appropriate pin (

Table 6

RD or

WR); the two operations are mutually exclusive. The read or write

data is transported on the D7 to D0 pins. The correlation between

the D7 to D0 data bits and their functionality at a specific register

address is detailed in the register map (see

) and register

bit description.

Table 6

Parallel I/O operation allows write access to each byte of any

Readback capability is slower than write capability. It is intended as

a low speed function for debug purposes. Timing for both write

and read cycles is depicted in Figure 35 and Figure 36.

tWRHIGH

tWRLOW

tAHU

tDHU

tDSU

tASU

tWR

tASU

tDSU

tAHU

tDHU

tWRLOW

tWRHIGH

tWR

SPECIFICATION

3ns

3.5ns

0ns

3ns

6ns

9ns

VALUE

ADDRESS SETUP TIME TO WR SIGNAL ACTIVE

DATA SETUP TIME TO WR SIGNAL INACTIVE

ADDRESS HOLD TIME TO WR SIGNAL INACTIVE

DATA HOLD TIME TO WR SIGNAL INACTIVE

WR SIGNAL MINIMUM LOW TIME

WR SIGNAL MINIMUM HIGH TIME

WR SIGNAL MINIMUM PERIOD

DESCRIPTION

D[7:0]

ADDR[5:0]

Figure 35. I/O Port Write Cycle Timing (Parallel)

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