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AD9858

Rev. C | Page 14 of 32

THEORY OF OPERATION

The AD9858 DDS is a flexible device that can address a wide range

of applications. The device consists of a numerically controlled

oscillator (NCO) with a 32-bit phase accumulator, 14-bit phase

offset adjustment, a power efficient DDS core, and a 1 GSPS,

10-bit DAC. The AD9858 incorporates additional capabilities

for automated frequency sweeping. The device also offers an

analog mixer, a PFD, and a programmable CP with advanced fast

lock capability. These RF building blocks can be used for various

frequency synthesis loops or, as needed, in system design.

The AD9858 can directly generate frequencies up to 400 MHz

when driven at a 1 GHz internal clock speed. This clock can be

derived from an external clock source of up to 2 GHz by using

the on-chip, divide-by-2 feature. The on-chip mixer, PFD, and CP

make possible a variety of synthesizer configurations capable of

generating frequencies in the 1 GHz to 2 GHz range or higher.

The AD9858 offers the advantages of a DDS with the additional

flexibility to work in concert with analog frequency synthesis

techniques (PLL, mixing) to generate precision frequency signals

with high resolution, fast frequency hopping, fast settling time,

and automated frequency sweeping capabilities.

Writing data to its on-chip digital registers that control all

operations of the device easily configures the AD9858. The

AD9858 offers a choice of serial or parallel ports for controlling

the device. Four user profiles can be selected by a pair of

external pins. These profiles allow independent setting of the

frequency tuning word and the phase offset adjustment word

for each of the four selectable configurations.

The AD9858 can be programmed to operate in single-tone mode

or in frequency sweeping mode. To save on power consumption,

there is also a programmable full sleep mode, during which most

of the device is powered down to reduce current flow.

The operation of a direct digital synthesizer (DDS) is described

in detail in a tutorial available from Analog Devices at

www.analog.com/dds.

COMPONENT BLOCKS

DDS Core

The DDS core generates the numeric values that represent a

sinusoid in the digital domain. Depending on the operating

mode of the DDS, this sinusoid may be changed in frequency,

phase, or perhaps modulated by an information carrying signal.

The frequency of the output signal is determined by a user-

programmed frequency tuning word (FTW). The relation of

the output frequency of the device to the system clock (SYSCLK)

is determined by

()

OUT

SYSCLK

FTW

where

N = 32.

For a more detailed explanation of a DDS core, consult the DDS

tutorial at www.analog.com/dds.

DAC Output

The AD9858 includes a 10-bit current output DAC. Two

complementary outputs provide a combined full-scale output

current (IOUT, IOUT). Differential outputs reduce the amount

of common-mode noise that may be present at the DAC output,

offering the advantage of an increased signal-to-noise ratio (SNR).

The full-scale current is controlled by means of an external

resistor (RSET) connected between the DACISET pin and analog

ground. The full-scale current is proportional to the resistor

value as

RSET = 39.19/IOUT

The maximum full-scale output current of the combined DAC

outputs is 40 mA, but limiting the output to 20 mA provides the

best spurious-free dynamic range (SFDR) performance. The DAC

output compliance range is (AVDD − 1.5 V) to (AVDD + 0.5 V).

Voltages developed beyond this range cause excessive DAC

distortion and can damage the DAC output circuitry. Proper

attention should be paid to the load termination to keep the

output voltage within this compliance range. When terminating

the differential outputs into a transformer, the center tap should

be attached to AVDD.

PLL Frequency Synthesizer

The PLL frequency synthesizer is a group of independent

synthesis blocks designed to be used with the DDS to expand

the range of synthesis applications. These blocks are a digital

PFD that drives a CP. The charge pump incorporates fast locking

logic, described in the Fast Locking Logic section. Based on

system requirements, the user supplies an external loop filter

and VCO. A high speed analog mixer is included for translation

synthesis loops. Using the different blocks in the PLL frequency

synthesizer, in conjunction with the DDS, the user can create

translation loops (also known as offset loops), fractional divider

loops, and traditional PLL loops to multiply the output of the DDS

in frequency.

Phase Frequency Detector (PFD)

The phase frequency detector has two inputs: PDIN and DIVIN.

Both are analog inputs that can operate in differential mode or

single-ended mode. Both operate at frequencies up to 150 MHz,

although signals of up to 400 MHz can be accommodated on the

inputs when the divide-by-4 functions are used. The expected

input level for both PDIN and DIVIN is in the range of 800 mV p-p

(differential) and 400 mV p-p (single-ended). A programmable

divider that offers division ratios of M, N = {1, 2, 4} immediately

follows the input. The division ratio is controlled by means of

the control function register.

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