AD9858SLASHFDPCB datasheet(8/32 Pages) AD

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AD9858

Rev. C | Page 8 of 32

Pin No.

Mnemonic

I/O

Description

SDO

This is valid for serial programming mode only. When operating the I/O port as a 3-wire

serial port, this pin serves as a unidirectional serial data output pin. When operated as a 2-wire

serial port, this pin is unused.

SDIO

I/O

This is valid for serial programming mode only. When operating the I/O port as a 3-wire serial

port, this pin is the serial data input. When operated as a 2-wire serial port, this pin is the

bidirectional serial data pin.

WR/SCLK

When the I/O port is configured for parallel programming mode, this pin functions as an active

low write pulse (WR). When configured for serial programming mode, this pin functions as the

serial data clock (SCLK).

RD/CS

When the I/O port is configured for parallel programming mode, this pin functions as an active

low read pulse (RD). When configured for serial programming mode, this pin functions as an

active low chip select (CS) that allows multiple devices to share the serial bus.

29, 30, 37 to 39,

41, 42, 49, 50, 52,

69, 74, 80, 85, 87, 88

AGND

Analog Ground.

31, 32, 35, 36,

40, 43, 44, 47,

48, 51, 70, 73,

77, 86, 89, 90

AVDD

Analog Supply Voltage.

REFCLK

Reference Clock Complementary Input. When the REFCLK port operates in single-ended mode,

REFCLK should be decoupled to AVDD with a 0.1 μF capacitor.

REFCLK

Reference Clock Input.

Mixer Local Oscillator (LO) Complementary Input. When the LO port operates in single-ended

mode, LO should be decoupled to AVDD with a 0.1 μF capacitor.

Mixer Local Oscillator (LO) Input.

Analog Mixer RF Complementary Input. When the RF port operates in single-ended mode,

RF should be decoupled to AVDD with a 0.1 μF capacitor.

Analog Mixer RF Input.

Analog Mixer IF Output.

Analog Mixer IF Complementary Output.

PFD

Phase Frequency Detector Complementary Input. When the PFD port operates in single-ended

mode, PFD should be decoupled to AVDD with a 0.1 μF capacitor.

PFD

Phase Frequency Detector Input.

59, 60, 75, 76

No Connection.

CPISET

Charge Pump Output Current Control. A resistor connected from CPISET to CPGND establishes

the reference current for the charge pump.

62, 67

CPVDD

Charge Pump Supply Voltage.

63, 68

CPGND

Charge Pump Ground.

CPFL

Charge Pump Fast Lock Output.

65, 66

Charge Pump Output.

DIV

Phase Frequency Detector Feedback Input.

DIV

Phase Frequency Detector Feedback Complementary Input. When the DIV port operates in

single-ended mode, DIV should be decoupled to AVDD with a 0.1 μF capacitor.

DACBP

DAC Baseline Decoupling Pin. Typically bypassed to Pin 77 with a 0.1 μF capacitor.

DACISET

A resistor connected from DACISET to AGND establishes the reference current for the DAC.

81, 82

IOUT

DAC Output.

83, 84

IOUT

DAC Complementary Output.

SPSELECT

I/O Port Serial/Parallel Programming Mode Select Pin. Logic 0 is serial programming mode, and

Logic 1 is parallel programming mode.

RESET

Active High Hardware Reset Pin. Assertion of the RESET pin forces the AD9858 to its default

operating conditions.

97, 98

PS0, PS1

Used to select one of the four internal profiles. These pins are synchronous to the SYNCLK output.

FUD

Frequency Update. The rising edge transfers the contents of the internal buffer registers to the

memory registers. This pin is synchronous to the SYNCLK output.

100

SYNCLK

Clock Output Pin. Serves as a synchronizer for external hardware. SYNCLK runs at REFCLK/8.

EPAD

Exposed paddle must be soldered to ground.

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