AD9915SLASHPCBZ datasheet(27/51 Pages) AD

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Data Sheet

AD9915

FUNCTIONAL BLOCK DETAIL

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Normal Ramp Generation

Normal ramp generation implies that both no-dwell bits are cleared

(see the No-Dwell Ramp Generation section for details). In Figure

38, a sample ramp waveform is depicted with the required control

signals. The top trace is the DRG output. The next trace down

is the status of the DROVER output pin (assuming that the DRG

over output enable bit is set). The remaining traces are control bits

and control pins. The pertinent ramp parameters are also identified

(upper and lower limits plus step size and Δt for the positive

and negative slopes). Along the bottom, circled numbers identify

specific events. These events are referred to by number (Event 1

and so on) in the following paragraphs.

In this example, the positive and negative slopes of the ramp are

different to demonstrate the flexibility of the DRG. The parameters

of both slopes can be programmed to make the positive and

negative slopes the same.

Event 1—The digital ramp enable bit is set, which has no effect on

the DRG output because the bit is not effective until an input/output

update occurs.

Event 2—An input/output update registers the digital ramp enable

bit. If DRCTL = 1 is in effect (the gray portion of the DRCTL

trace), the DRG output immediately begins a positive slope (the

gray portion of the DRG output trace). Otherwise, if DRCTL = 0, the

DRG output is initialized to the lower limit.

Event 3—DRCTL transitions to Logic 1 to initiate a positive slope

at the DRG output. In this example, the DRCTL pin is held long

enough to cause the DRG to reach the programmed upper limit.

The DRG remains at the upper limit until the ramp accumulator

is cleared (DRCTL = 0) or the upper limit is reprogrammed to a

higher value. In the latter case, the DRG immediately resumes the

previous positive slope profile.

Event 4—DRCTL transitions to Logic 0 to initiate a negative slope

at the DRG output. In this example, the DRCTL pin is held long

enough to cause the DRG to reach the programmed lower limit.

The DRG remains at the lower limit until DRCTL = 1, or until the

lower limit is reprogrammed to a lower value. In the latter case, the

DRG immediately resumes the previous negative slope profile.

Event 5—DRCTL transitions to Logic 1 for the second time, initiat-

ing a second positive slope.

Event 6—The positive slope profile is interrupted by DRHOLD tran-

sitioning to Logic 1. This stalls the ramp accumulator and freezes

the DRG output at the last value.

Event 7—DRHOLD transitions to Logic 0, releasing the ramp accu-

mulator and reinstating the previous positive slope profile.

Event 8—The clear digital ramp accumulator bit is set, which has

no effect on the DRG because the bit is not effective until an

input/output update is issued.

Event 9—An input/output update registers that the clear digital

ramp accumulator bit is set, resetting the ramp accumulator and

forcing the DRG output to the programmed lower limit. The DRG

output remains at the lower limit until the clear condition is re-

moved.

Event 10—The clear digital ramp accumulator bit is cleared, which

has no effect on the DRG output because the bit is not effective

until an input/output update is issued.

Event 11—An input/output update registers that the clear digital

ramp accumulator bit is cleared, releasing the ramp accumulator;

and the previous positive slope profile restarts.

Event 12—The autoclear digital ramp accumulator bit is set, which

has no effect on the DRG output because the bit is not effective

until an input/output update is issued.

Event 13—An input/output update registers that the autoclear digital

ramp accumulator bit is set, resetting the ramp accumulator. How-

ever, with an automatic clear, the ramp accumulator is held in reset

for only a single DDS clock cycle. This forces the DRG output to the

lower limit, but the ramp accumulator is immediately made available

for normal operation. In this example, the DRCTL pin remains Logic

1; therefore, the DRG output restarts the previous positive ramp

profile.

No-Dwell Ramp Generation

The no-dwell high (0x01[18]) and no-dwell low (0x01[17]) bits add

to the flexibility of the DRG capabilities. During normal (default)

ramp generation, when the DRG output reaches the programmed

upper or lower limit, it simply remains at the limit until the operating

parameters dictate otherwise. However, during no-dwell operation,

the DRG output does not necessarily remain at the limit. For ex-

ample, during no-dwell high operation (0x01[18:17] = 10 (binary)),

when the DRG reaches its upper limit, the DRG immediately snaps

to the lower limit and halts. Likewise, during no-dwell low operation

(0x01[18:17] = 01 (binary)), when the DRG reaches its lower limit,

the DRG immediately snaps to the upper limit and halts. Alterna-

tively, a continuous ramping mode is in effect when 0x01[18:17] =

11 (binary), in which case the DRG output automatically oscillates

between the upper and lower limits using the programmed slope

parameters.

Note that in continuous ramping mode, the DROVER signal oper-

ates differently than in dwell operation. In dwell operation, the

DROVER signal assumes a static Logic 1 state indicating the end

of the sweep. In continuous ramping mode, however, the DROVER

signal is a positive pulse (with a period of two cycles of the DDS

clock) that occurs each time the DRG output reaches either of the

programmed limits (assuming that the DRG over output enable bit

(0x01[13]) is set).

A no-dwell high DRG output waveform is shown in Figure 39. The

waveform diagram assumes that the digital ramp no-dwell high bit

is set and has been registered by an input/output update. The

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