AD9915SLASHPCBZ datasheet(40/51 Pages) AD

40 / 51 page

Data Sheet

AD9915

analog.com

Rev. G | 40 of 51

Table 17. Register Map

(Serial Address)

Bit Range

(Parallel

Address)

Bit 7

(MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0 (LSB)

Default

Value

(Hex)1

CFR1—Control

Function Register

1 (0x00)

[7:0] (0x00)

Digital

power-

down

DAC power-

down

REF CLK

input power-

down

Open

External power-

down control

Open

SDIO input

only

LSB first

mode

0x08

[15:8]

(0x01)

Load LRR

on input/

output

update

Autoclear

digital ramp

accumulator

Autoclear

phase

accumulator

Clear digital

ramp

accumulator

Clear phase

accumulator

Open

External OSK

enable

OSK enable

0x00

[23:16]

(0x02)

Open

Parallel port

streaming

enable

Enable sine

output

0x01

[31:24]

(0x03)

Open

VCO cal

enable

0x00

CFR2—Control

Function Register

2 (0x01)

[7:0](0x04)

Open

0x00

[15:8]

(0x05)

Matched

latency

enable

Frequency

jump enable

DRG over

output enable

Open

SYNC_CLK

enable

SYNC_CLK

invert

SYNC_OUT

source select

Sync

generator

active

0x09

[23:16]

(0x06)

Profile

mode

enable

Parallel data

port enable

Digital ramp destination

Digital ramp

enable

Digital ramp

no-dwell high

Digital ramp

no-dwell low

Programmable

modulus

enable

0x00

[31:24]

(0x07)

Open

0x00

CFR3—Control

Function Register

3 (0x02)

[7:0](0x08)

Open

Manual ICP

selection

ICP[2:0]

Lock detect

enable

Minimum LDW[1:0]

0x1C

[15:8]

(0x09)

Feedback Divider N[7:0]

0x19

[23:16]

(0x0A)

Open

PLL input

divider reset

PLL input divide value[1:0]

PLL input

doubler select

PLL enable

PLL input

divider select

PLL edge

select

0x00

[31:24]

(0x0B)

Open

0x00

CFR4—Control

Function Register

4 (0x03)

[7:0](0x0C)

Requires register default value settings (0x20)

0x20

[15:8]

(0x0D)

Requires register default value settings (0x21)

0x21

[23:16]

(0x0E)

Requires register default value settings (0x05)

0x05

[31:24]

(0x0F)

Open

Auxiliary

divider

power-down

DAC CAL

clock power-

down

DAC CAL

enable2

0x00

Digital Ramp

Lower Limit

[7:0] (0x10)

Digital ramp lower limit[7:0]

0x00

[15:8] (0x11)

Digital ramp lower limit[15:8]

0x00

[23:16]

(0x12)

Digital ramp lower limit[23:16]

0x00

[31:24]

(0x13)

Digital ramp lower limit[31:24]

0x00

Digital Ramp

Upper Limit

[7:0] (0x14)

Digital ramp upper limit[7:0]

0x00

[15:8]

(0x15)

Digital ramp upper limit[15:8]

0x00

[23:16]

(0x16)

Digital ramp upper limit[23:16]

0x00

[31:24]

(0x17)

Digital ramp upper limit[31:24]

0x00

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