AD9915SLASHPCBZ datasheet(17/51 Pages) AD

17 / 51 page

Data Sheet

AD9915

THEORY OF OPERATION

analog.com

Rev. G | 17 of 51

The AD9915 has five modes of operation.

►

Single tone

►

Profile modulation

►

Digital ramp modulation (linear sweep)

►

Parallel data port modulation

►

Programmable modulus mode

The modes define the data source that supplies the DDS with

the signal control parameters: frequency, phase, or amplitude. The

partitioning of the data into different combinations of frequency,

phase, and amplitude is established based on the mode and/or

specific control bits and function pins.

Although the various modes are described independently, they can

be enabled simultaneously. This provides an unprecedented level

of flexibility for generating complex modulation schemes. However,

to avoid multiple data sources from driving the same DDS signal

control parameter, the device has a built in priority protocol.

In single tone mode, the DDS signal control parameters come

directly from the profile programming registers. In digital ramp mod-

ulation mode, the DDS signal control parameters are delivered by

a digital ramp generator. In parallel data port modulation mode, the

DDS signal control parameters are driven directly into the parallel

port.

The various modulation modes generally operate on only one of

the DDS signal control parameters (two in the case of the polar

modulation format via the parallel data port). The unmodulated DDS

signal control parameters are stored in programming registers and

automatically routed to the DDS based on the selected mode.

A separate output shift keying (OSK) function is also available.

This function employs a separate digital linear ramp generator that

affects only the amplitude parameter of the DDS. The OSK function

has priority over the other data sources that can drive the DDS

amplitude parameter. As such, no other data source can drive the

DDS amplitude when the OSK function is enabled.

SINGLE TONE MODE

In single tone mode, the DDS signal control parameters are sup-

plied directly from the profile programming registers. A profile is an

independent register that contains the DDS signal control parame-

ters. Eight profile registers are available. Note that the profile pins

must select the desired register.

PROFILE MODULATION MODE

Each profile is independently accessible. For FSK, PSK, or ASK

modulation, use the three external profile pins (PS[2:0]) to select

the desired profile. A change in the state of the profile pins with

the next rising edge on SYNC_CLK updates the DDS with the

parameters specified by the selected profile.

Therefore, the profile change must meet the setup and hold times

to the SYNC_CLK rising edge. Note that amplitude control must

also be enabled via the OSK enable bit in the CFR1 register

(0x00[8]).

DIGITAL RAMP MODULATION MODE

In digital ramp modulation mode, the DRG directly modulates one

of the DDS signal control parameters (frequency, phase, or ampli-

tude) via a dedicated 32-bit sweep accumulator (the sweep accu-

mulator is completely independent of the 32-bit phase accumulator

in the DDS core). The user controls the characteristics of a ramp

(for example, sweep range, step size, and step rate) by program-

ming the appropriate registers via the serial or parallel input/output

port. The registers provide the user with the ability to control the

rising and falling characteristics of a ramp independently.

The ramp is digitally generated via the 32-bit sweep accumulator

within the DRG. The user can program the digital ramp generator

(DRG) to direct the 32-bit output of the sweep accumulator to

affect the frequency, phase, or amplitude parameter of the DDS.

When programmed for a frequency sweep, all 32 bits of the sweep

accumulator are delivered to the DDS for frequency control. When

programmed for a phase sweep, the 16 LSBs of the sweep accu-

mulator are delivered to the DDS for phase control. Therefore, for

a phase sweep, the 16 MSBs of the 32-bit registers normally used

for frequency sweeping must be programmed with zeros. When

programmed for an amplitude sweep, the 12 LSBs of the sweep

accumulator are delivered to the DDS for amplitude control. There-

fore, for an amplitude sweep, the 20 MSBs of the 32-bit registers

normally used for frequency sweeping must be programmed with

zeros.

The ramp direction (rising or falling) is externally controlled by

the DRCTL pin. The user can also suspend the operation of the

ramp generator by asserting the DRHOLD pin. Note that the DRG

requires the amplitude control of the DDS to be enabled via the

OSK enable bit in Register CFR1.

PARALLEL DATA PORT MODULATION MODE

In parallel data port modulation mode, the modulated DDS signal

control parameter(s) are supplied directly from the 32-bit parallel

data port. The function pins define how the 32-bit data-word is

applied to the DDS signal control parameters. Formatting of the

32-bit data-word is unsigned binary, regardless of the destination.

Parallel Data Clock (SYNC_CLK)

The AD9915 has an internal clock signal (SYNC_CLK) that runs at

1/16 of the DAC sample rate. SYNC_CLK is the primary internal

timing signal of the AD9915. For example, the PS[2:0] pins, DRCTL

pin, and DRHOLD pin are all gated internally by SYNC_CLK.

In parallel data port modulation mode (CFR2[22] = 1), the AD9915

uses the rising edge of SYNC_CLK to capture the logic level

applied to the D[31:0] pins and the F[3:0] pins. Thus, the parallel

data port essentially operates at the SYNC_CLK rate in parallel

data port modulation mode.

AD9915/PCBZ Scheda tecnica(PDF) 17 Page - Analog Devices

AD9915/PCBZ Scheda tecnica(HTML) 17 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51

Scheda tecnica Scarica

Link URL