AD9915SLASHPCBZ datasheet(46/51 Pages) AD

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Data Sheet

AD9915

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Rev. G | 46 of 51

Table 18. Bit Description for CFR1

Bits

Mnemonic

Description

1 = assertion of the EXT_PWR_DWN pin affects power-down (default).

Open

Open.

SDIO input only

0 = configures the SDIO pin for bidirectional operation; 2-wire serial programming

mode (default).

1 = configures the serial data input/output pin (SDIO) as an input only pin; 3-wire serial

programming mode.

LSB first mode

0 = configures the serial input/output port for MSB-first format (default).

1 = configures the serial input/output port for LSB-first format.

Control Function Register 2 (CFR2)—Address 0x01

Table 19. Bit Descriptions for CFR2

Bit(s)

Mnemonic

Description

[31:24]

Open

Profile mode enable

0 = disables profile mode functionality (default).

1 = enables profile mode functionality. Profile pins select the desired profile.

Parallel data port enable

See the Parallel Data Port Modulation Mode section for more details.

0 = disables parallel data port modulation functionality (default).

1 = enables parallel data port modulation functionality.

[21:20]

Digital ramp destination

See Table 9 for details. Default is 00. See the Digital Ramp Generator (DRG) section for more details.

Digital ramp enable

0 = disables digital ramp generator functionality (default).

1 = enables digital ramp generator functionality.

Digital ramp no-dwell high

See the Digital Ramp Generator (DRG) section for details.

0 = disables no-dwell high functionality (default).

1 = enables no-dwell high functionality.

Digital ramp no-dwell low

See the Digital Ramp Generator (DRG) section for details.

0 = disables no-dwell low functionality (default).

1 = enables no-dwell low functionality.

Programmable modulus enable

0 = disables programmable modulus.

1 = enables programmable modulus.

Matched latency enable

0 = simultaneous application of amplitude, phase, and frequency changes to the DDS arrive at the output at different

times based on their individual path latency listed in Table 2 under data latency (pipe line delay) (default).

1 = simultaneous application of amplitude, phase, and frequency changes to the DDS arrive at the output

simultaneously.

Frequency jump enable

0 = disables frequency jump mode (default).

1 = enables frequency jump mode. Must have the digital generator DRG enabled for this feature.

DRG over output enable

0 = disables the DROVER output.

1 = enables the DROVER output.

Open

Open.

SYNC_CLK enable

0 = the SYNC_CLK pin is disabled and forced to a static Logic 0 state; the internal clock signal continues to operate

and provide timing.

1 = the internal SYNC_CLK signal appears at the SYNC_CLK pin (default).

SYNC_CLK invert

0 = normal SYNC_CLK pin polarity (default).

1 = inverted SYNC_CLK pin polarity.

SYNC_OUT source select

0 = the SYNC_IN signal routes to the SYNC_OUT pin.

1 = the sync out generator routes to the SYNC_OUT pin (see CFR2[8]).

Sync generator active

0 = the sync out generator outputs static Logic 0.

1 = the sync out generator outputs sync pulses.

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