AD9915SLASHPCBZ datasheet(6/51 Pages) AD

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Data Sheet

AD9915

SPECIFICATIONS

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Rev. G | 6 of 51

AC SPECIFICATIONS

AVDD (1.8 V) and DVDD (1.8 V) = 1.8 V ± 5%, AVDD3 (3.3 V) and DVDD_I/O (3.3 V) = 3.3 V ± 5%, TA = 25°C, RSET = 3.3 kΩ, IOUT = 20 mA,

external reference clock frequency = 2.5 GHz with reference clock (REF CLK) multiplier bypassed, unless otherwise noted.

Table 2.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

REF CLK INPUT

Input frequency range

REF CLK Multiplier Bypassed

Input Frequency Range

500

2500

MHz

Maximum fOUT is 0.4 × fSYSCLK

Duty Cycle

Minimum Differential Input Level

632

mV p-p

Equivalent to 316 mV swing on each leg

System Clock (SYSCLK) PLL Enabled

VCO Frequency Range

2400

2500

MHz

VCO Gain (KV)

MHz/V

Maximum PFD Rate

125

MHz

CLOCK DRIVERS

SYNC_CLK Output Driver

Frequency Range

156

MHz

Duty Cycle

Rise Time/Fall Time (20% to 80%)

650

SYNC_OUT Output Driver

10 pF load

Frequency Range

6.5

MHz

Duty Cycle

CFR2 register, Bit 9 = 1

Rise Time (20% to 80%)

1350

10 pF load

Fall Time (20% to 80%)

1670

10 pF load

DAC OUTPUT CHARACTERISTICS

Output Frequency Range (1st Nyquist Zone)

1250

MHz

Output Resistance

Single-ended (each pin internally terminated to AVDD (3.3

V))

Output Capacitance

Full-Scale Output Current

20.48

Range depends on DAC RSET resistor

Gain Error

−10

+10

% FS

Output Offset

0.6

μA

Voltage Compliance Range

AVDD − 0.50

AVDD + 0.50 V

Wideband SFDR

See the Typical Performance Characteristics section

122.5 MHz Output

−67

dBc

0 MHz to 1250 MHz

305.3 MHz Output

−66

dBc

0 MHz to 1250 MHz

497.5 MHz Output

−59

dBc

0 MHz to 1250 MHz

978.2 MHz Output

−60

dBc

0 MHz to 1250 MHz

Narrow-Band SFDR

See the Typical Performance Characteristics section

122.5 MHz Output

−95

dBc

±500 kHz

305.3 MHz Output

−95

dBc

±500 kHz

497.5 MHz Output

−95

dBc

±500 kHz

978.2 MHz Output

−92

dBc

±500 kHz

DIGITAL TIMING SPECIFICATIONS

Time Required to Enter Power-Down

Power-down mode loses DAC/PLL calibration settings

Time Required to Leave Power-Down

250

Must recalibrate DAC/PLL

Minimum Master Reset time

SYSCLK cycles

Maximum DAC Calibration Time (tCAL)

188

µs

See the DAC Calibration Output section for formula; Bit 6

in Register 0x1B = 0

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