AD9915SLASHPCBZ datasheet(11/51 Pages) AD

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Data Sheet

AD9915

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

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Rev. G | 11 of 51

Table 5. Pin Function Descriptions

Pin No.

Mnemonic

I/O1

Description

D0/CS/PWD

Parallel Port Pin/Chip Select/Parallel Width. This pin is D0 for direct FSK, PSK, or ASK data. If serial mode is

invoked via F0 to F3, this pin is used for the chip select for serial operation. If parallel mode is enabled, this pin sets

either 8-bit data or 16-bit data.

6, 23, 73

DVDD (1.8V)

Digital Core Supplies (1.8 V).

7, 17, 24, 74, 84

DGND

Digital Ground.

16, 83

DVDD_I/O (3.3V)

Digital Input/Output Supplies (3.3 V).

32, 56, 57

AVDD (1.8V)

Analog Core Supplies (1.8 V).

33, 35, 37, 38, 44, 46,

49, 51

AGND

Analog Ground.

34, 36, 39, 40, 43, 47,

50, 52, 53, 60

AVDD (3.3V)

Analog DAC Supplies (3.3 V).

25, 26, 27

PS0 to PS2

Profile Select Pins. Digital inputs (active high). Use these pins to select one of eight phase/frequency profiles for

the DDS. Changing the state of one of these pins transfers the current contents of all input/output buffers to the

corresponding registers. State changes must be set up on the SYNC_CLK pin (Pin 82).

28, 29, 30, 31

F0 to F3

Function Pins. Digital inputs. The state of these pins determines if a serial or parallel interface is used. In addition,

the function pins determine how the 32-bit parallel data-word is partitioned for FSK, PSK, or ASK modulation mode.

AOUT

DAC Complementary Output Source. Analog output (voltage mode). Internally connected through a 50 Ω resistor to

AVDD (3.3 V).

AOUT

DAC Output Source. Analog output (voltage mode). Internally connected through a 50 Ω resistor to AVDD (3.3 V).

DAC_BP

DAC Bypass Pin. Provides access to the common control node of the DAC current sources. Connecting a capacitor

between this pin and ground can improve noise performance at the DAC output.

DAC_RSET

Analog Reference. This pin programs the DAC output full-scale reference current. Connect a 3.3 kΩ resistor to

AGND.

REF_CLK

Complementary Reference Clock Input. Analog input.

REF_CLK

Reference Clock Input. Analog input.

LOOP_FILTER

External PLL Loop Filter Node.

REF

Local PLL Reference Supply. Typically at 2.05 V.

SYNC_OUT

Digital Synchronization Output. Clock source (output) for synchronizing multiple chips.

SYNC_IN

Digital Synchronization Input. Clock receiver (input) for synchronizing multiple chips.

DRCTL

Ramp Control. Digital input (active high). This pin controls the sweep direction (up/down).

DRHOLD

Ramp Hold. Digital input (active high). Pauses the sweep when active.

DROVER

Ramp Over. Digital output (active high). This pin switches to Logic 1 when the digital ramp generator reaches the

programmed upper or lower limit.

OSK

Output Shift Keying. Digital input (active high). When the OSK features are placed in either manual or automatic

mode, this pin controls the OSK function. In manual mode, it toggles the multiplier between 0 (low) and the

programmed amplitude scale factor (high). In automatic mode, a low sweeps the amplitude down to zero and a high

sweeps the amplitude up to the amplitude scale factor. This pin is functional only when enabled via a register bit.

EXT_PWR_DWN

External Power-Down. Digital input (active high). A high level on this pin initiates the currently programmed

power-down mode.

SYNC_CLK

Clock Output. Digital output. Many of the digital inputs on the chip, such as I/O_UPDATE, PS[2:0], and the parallel

data port (D0 to D31), must be set up on the rising edge of this signal.

MASTER_RESET

Master Reset. Digital input (active high). Clears all memory elements and sets registers to default values.

I/O_UPDATE

Input/Output Update. Digital input (active high). A high on this pin transfers the contents of the input/output buffer

registers to their corresponding active registers.

EPAD

Exposed Pad. The EPAD must be soldered to ground.

1 I means input, O means output, and I/O means input/output.

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