AD9915SLASHPCBZ datasheet(45/51 Pages) AD

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Data Sheet

AD9915

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Rev. G | 45 of 51

Control Function Register 1 (CFR1)—Address 0x00

Table 18. Bit Description for CFR1

Bits

Mnemonic

Description

[31:25]

Open

VCO cal enable

1 = initializes the auto internal PLL calibration. The calibration is required if the PLL is to provide the internal system

clock. Must first be reset to Logic 0 before another calibration can be issued.

[23:18]

Open

Open.

Parallel port streaming enable

0 = the 32 bit parallel port needs an input/output update to activate or register any FTW, POW, or AMP data presented

to the 32-bit parallel port.

1 = the parallel port continuously samples data on the 32 input pins using SYNC_CLK and multiplexes the value of

FTW/POW/AMP accordingly, per the configuration of the F0 to F3 pins, without the need of an input/output update.

Data must meet the setup and hold times of the SYNC_CLK rising edge. If the function pins are used dynamically to

alter data between parameters, they must also meet the timing of the SYNC_CLK edge.

Enable sine output

0 = cosine output of the DDS is selected.

1 = sine output of the DDS is selected (default).

Load LRR on input/output update

Ineffective unless CFR2[19] = 1.

0 = normal operation of the digital ramp timer (default).

1 = interrupts the digital ramp timer operation to load a new linear ramp rate (LRR) value any time I/O_UPDATE is

asserted or a PS[2:0] change occurs.

Autoclear digital ramp accumulator

0 = normal operation of the DRG accumulator (default).

1 = the digital ramp accumulator is reset for one cycle of the DDS clock (SYNC_CLK), after which the accumulator

automatically resumes normal operation. As long as this bit remains set, the ramp accumulator is momentarily reset

each time an input/output update is asserted or a PS[2:0] change occurs. This bit is synchronized with either an

input/output update or a PS[2:0] change and the next rising edge of SYNC_CLK.

Autoclear phase accumulator

0 = normal operation of the DDS phase accumulator (default).

1 = synchronously resets the DDS phase accumulator anytime I/O_UPDATE is asserted or a profile change occurs.

Clear digital ramp accumulator

0 = normal operation of the digital ramp generator (default).

1 = asynchronous, static reset of the DRG accumulator. The ramp accumulator remains reset as long as this bit

remains set. This bit is synchronized with either an input/output update or a PS[2:0] change and the next rising edge of

SYNC_CLK.

Clear phase accumulator

0 = normal operation of the DDS phase accumulator (default).

1 = asynchronous, static reset of the DDS phase accumulator as long as this bit is set. This bit is synchronized with

either an input/output update or a PS[2:0] change and the next rising edge of SYNC_CLK.

Open

Open.

External OSK enable

0 = manual OSK enabled (default).

1 = automatic OSK enabled.

Ineffective unless CFR1[8] = 1.

OSK enable

0 = OSK disabled (default).

1 = OSK enabled. This bit must be set to affect any digital amplitude change using the DRG, a profile, direct mode via

the 32-bit parallel port, or OSK pin.

Digital power-down

This bit is effective without the need for an input/output update.

0 = clock signals to the digital core are active (default).

1 = clock signals to the digital core are disabled.

DAC power-down

0 = DAC clock signals and bias circuits are active (default).

1 = DAC clock signals and bias circuits are disabled.

REFCLK input power-down

This bit is effective without the need for an input/output update.

0 = REFCLK input circuits and PLL are active (default).

1 = REFCLK input circuits and PLL are disabled.

Open

Open.

External power-down control

0 = assertion of the EXT_PWR_DWN pin affects fast recovery power-down.

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