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TDA4VEN...Q1 Scheda tecnica(PDF) 85 Page - Texas Instruments

Il numero della parte TDA4VEN...Q1
Spiegazioni elettronici  TDA4VEN, TDA4AEN Jacinto™ Processors
PDF  236 Pages
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Produttore elettronici  TI [Texas Instruments]
Homepage  http://www.ti.com
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TDA4VEN...Q1 Scheda tecnica(HTML) 85 Page - Texas Instruments

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over operating junction temperature range (unless otherwise noted)
SUPPLY NAME
DESCRIPTION
MIN(1)
NOM
MAX(1)
UNIT
VDDSHV0
Dual-voltage IO supply for IO group 0
1.8-V operation
1.71
1.8
1.89
V
3.3-V operation
3.135
3.3
3.465
V
VDDSHV1
Dual-voltage IO supply for IO group 1
1.8-V operation
1.71
1.8
1.89
V
3.3-V operation
3.135
3.3
3.465
V
VDDSHV2
Dual-voltage IO supply for IO group 2
1.8-V operation
1.71
1.8
1.89
V
3.3-V operation
3.135
3.3
3.465
V
VDDSHV3
Dual-voltage IO supply for IO group 3
1.8-V operation
1.71
1.8
1.89
V
3.3-V operation
3.135
3.3
3.465
V
VDDSHV5
Dual-voltage IO supply for IO group 5
1.8-V operation
1.71
1.8
1.89
V
3.3-V operation
3.135
3.3
3.465
V
VDDSHV6
Dual-voltage IO supply for IO group 6
1.8-V operation
1.71
1.8
1.89
V
3.3-V operation
3.135
3.3
3.465
V
TJ
Operating junction temperature range
Automotive Q100
–40
125
°C
Extended Industrial
–40
105
°C
(1)
The voltage at the device ball must never drop below the MIN voltage or rise above the MAX voltage for any amount of time during
normal device operation.
(2)
VDD_CORE, VDDA_CORE_CSI_DSI, VDDA_CORE_DSI_CLK, VDDA_CORE_USB, and VDDA_DDR_PLL0 shall be sourced from
the same power source. Care should be taken to ensure that voltage differential between VDD_CORE and VDDA_CORE_USB is
within +/- 1%.
(3)
VDD_CANUART shall be connected to an always on power source when using Partial IO or IO Only + DDR Self-refresh low power
modes. VDD_CANUART shall be connected to the same power source as VDD_CORE, VDDA_CORE_CSI_DSI, VDDA_CORE_USB,
and VDDA_DDR_PLL0 when not using Partial IO or IO Only + DDR Self-refresh low power modes.
(4)
VDD_MMC0 and VDDA_0P85_DLL_MMC0 must be connected to the same power source as VDD_CORE when MMC0 is not used. In
this case, VDD_MMC0 and VDDA_0P85_DLL_MMC0 may be operated at a nominal voltage of 0.75 or 0.85.
(5)
VDDS_DDR and VDDS_DDR_C shall be sourced from the same power source.
(6)
Refer to the Recommended Operating Conditions for OTP eFuse Programming table for VPP supply voltages based on eFuse usage.
(7)
The VMON_VSYS pin provides a way to monitor the system power supply. For more information, see System Power Supply Monitor
Design Guidelines.
(8)
An external resistor divider is required to limit the voltage applied to this device pin. For more information, see USB VBUS Design
Guidelines.
(9)
VDDSHV_CANUART shall be connected to an always on power source when using Partial IO or IO Only + DDR Self-refresh low
power modes. VDDSHV_CANUART shall be connected to any valid IO power source when not using Partial IO or IO Only + DDR
Self-refresh low power modes.
www.ti.com
TDA4VEN-Q1, TDA4AEN-Q1
SPRSP96A – MARCH 2024 – REVISED SEPTEMBER 2024
Copyright © 2024 Texas Instruments Incorporated
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