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TDA4VEN...Q1 Scheda tecnica(PDF) 142 Page - Texas Instruments |
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TDA4VEN...Q1 Scheda tecnica(HTML) 142 Page - Texas Instruments |
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142 / 236 page ![]() 6.9.5.13 GPMC For more details about features and additional description information on the device General-Purpose Memory Controller, see the corresponding subsections within Signal Descriptions and Detailed Description sections. Table 6-64 presents timing conditions for GPMC. Table 6-64. GPMC Timing Conditions PARAMETER MIN MAX UNIT INPUT CONDITIONS SRI Input slew rate 1.65 4 V/ns OUTPUT CONDITIONS CL Output load capacitance 2 20 pF PCB CONNECTIVITY REQUIREMENTS td(Trace Delay) Propagation delay of each trace 133MHz Synchronous Mode 140 360 ps All other modes 140 720 ps td(Trace Mismatch Delay) Propagation delay mismatch across all traces 200 ps For more information, see General-Purpose Memory Controller (GPMC) section in Peripherals chapter in the device TRM. 6.9.5.13.1 GPMC and NOR Flash — Synchronous Mode Table 6-65 and Table 6-66 present timing requirements and switching characteristics for GPMC and NOR Flash - Synchronous Mode. Table 6-65. GPMC and NOR Flash Timing Requirements — Synchronous Mode see Figure 6-47, Figure 6-48, and Figure 6-51 NO. PARAMETER DESCRIPTION MODE(4) MIN MAX MIN MAX UNIT GPMC_FCLK = 100MHz(1) GPMC_FCLK = 133MHz(1) F12 tsu(dV-clkH) Setup time, input data GPMC_AD[15:0] valid before output clock GPMC_CLK high div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1 1.61 0.92 ns not_div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1 0.86 3.41 ns F13 th(clkH-dV) Hold time, input data GPMC_AD[15:0] valid after output clock GPMC_CLK high div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1 2.09 2.09 ns not_div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1 2.09 2.09 ns F21 tsu(waitV-clkH) Setup time, input wait GPMC_WAIT[j](2) (3) valid before output clock GPMC_CLK high div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1 1.61 0.92 ns not_div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1 0.86 3.41 ns F22 th(clkH-waitV) Hold time, input wait GPMC_WAIT[j](2) (3) valid after output clock GPMC_CLK high div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1 2.09 2.09 ns not_div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1 2.09 2.09 ns (1) GPMC_FCLK select TDA4VEN-Q1, TDA4AEN-Q1 SPRSP96A – MARCH 2024 – REVISED SEPTEMBER 2024 www.ti.com 142 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: TDA4VEN-Q1 TDA4AEN-Q1 |
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