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TDA4VEN...Q1 Scheda tecnica(PDF) 177 Page - Texas Instruments |
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TDA4VEN...Q1 Scheda tecnica(HTML) 177 Page - Texas Instruments |
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177 / 236 page ![]() Table 6-82 presents timing conditions for MMC0. Table 6-82. MMC0 Timing Conditions PARAMETER MIN MAX UNIT INPUT CONDITIONS SRI Input slew rate Legacy SDR High Speed SDR 0.3 0.9 V/ns High Speed DDR (CMD) 0.3 0.9 V/ns High Speed DDR (DAT) 0.45 0.9 V/ns OUTPUT CONDITIONS CL Output load capacitance HS400 1 6 pF All other modes 1 12 pF PCB CONNECTIVITY REQUIREMENTS td(Trace Delay) Propagation delay of each trace All modes 126 756 ps td(Trace Mismatch Delay) Propagation delay mismatch across all traces HS200 HS400 8 ps High Speed DDR 20 ps All other modes 100 ps www.ti.com TDA4VEN-Q1, TDA4AEN-Q1 SPRSP96A – MARCH 2024 – REVISED SEPTEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 177 Product Folder Links: TDA4VEN-Q1 TDA4AEN-Q1 |
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