SCANSTA101SMSLASHNOPB datasheet(13/42 Pages) TI2

13 / 42 page

SCANSTA101

www.ti.com

SNLS057J – MAY 2002 – REVISED APRIL 2013

If an interrupt enable is set then an interrupt will be generated. If an interrupt occurs at the same time as the

interrupt status is being read, then the interrupt will be set after the read is complete. All bits in the Interrupt

Status register are cleared when the register is read.

FLAG GENERATOR

The FG takes in the TDI_SM or TDO_SM pointer values from the PPI address pointers, compares them and

generates the appropriate flags. If a flag condition has occurred, it is passed, along with the corresponding load

enable, to the SIG to set the bit in the status register. If the flag condition changes, then the clear for the

corresponding bit is passed to the SIG to clear the flag. The TDO_SM empty and the TDI_SM full flags are

passed to the SSI also. A counter enable is passed from the SSI to indicate to the FG when the SSI's pointer

value has changed. If a decrement and an increment occur at the same time to either of the counters, the

counter value will not change.

PPI INTERFACE TIMING

The processor accesses to SCANSTA101 can be classified into six categories:

•

16-bit memory read

•

16-bit memory write

•

32-bit memory read

•

32-bit memory write

In 32-bit mode, only the LS word is used. The MS word is ignored. The timing for the 16-bit and 32-bit modes is

exactly the same.

The 16-bit mode memory write is accomplished by performing two consecutive register writes with the only

difference being that the actual write occurs on the second access. The 16-bit mode register read consists of two

accesses, with the first access performed similar to the 16-bit register read but requiring one more clock to

complete the memory access. Since all 32-bits of the memory data are captured on the first access, the second

memory read access is 2 clocks shorter than the first.

The processor initiates a write cycle by asserting CE followed by STB. A set time prior to asserting STB, the R/W

is driven low and the address and data buses are driven by valid address and data, respectively. After edge

detecting the STB and registering all the inputs, the address is decoded to determine which internal address

within the SCANSTA101 will be written by the processor. The DTACK will be asserted on the same rising edge

of SCK on which the negative edge of the STB signal is detected, indicating to the processor that it can deassert

the STB. When the SCANSTA101 detects the positive edge of the STB, it will deassert the DTACK indicating to

the processor that it can start a new cycle. The processor can start a new cycle by asserting the STB and by

driving the address and data buses with new address and data.

A read cycle is similar to the write cycle except that the DTACK will not be asserted until the selected address

location's contents are loaded. So, for a 16-bit register read it takes one more clock than it does for a write cycle.

Reads and writes to the SCANSTA101 memory require two consecutive accesses in the 16-bit external bus

mode. The memory writes are similar to register writes; the processor performs two consecutive 16-bit writes to

write to the selected memory location.

During a memory read, the DTACK line is not asserted until the contents of the memory is loaded into the

capture registers. For this reason the first read from the memory requires five clocks which includes the memory

access time, while the second read is done in three clock cycles.

SERIAL SCAN INTERFACE

The Serial Scan Interface consists of the following units:

•

Clock Divider and TCK_SM Control

•

TAP Tracker

•

Pointer Generator

•

Structure (Sequencer/Vector/Macro/ScanBridge) Decoder

Submit Documentation Feedback

Product Folder Links: SCANSTA101

SCANSTA101SM/NOPB Scheda tecnica(PDF) 13 Page - Texas Instruments

SCANSTA101SM/NOPB Scheda tecnica(HTML) 13 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42

Scheda tecnica Scarica

Link URL