SCANSTA101

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SNLS057J – MAY 2002 – REVISED APRIL 2013

WRITING AND READING PARTIAL LONG WORDS

Care should be taken when writing a partial long word to TDO_SM memory or reading a partial long word from

TDI_SM memory. Since the TDO_SM shifter shifts out LSB first, the valid (meaningful) bits within a partial long

word (i.e., long word containing less than 32 valid bits to be shifted to the scan chain) must be stored and written

into the memory as the least significant bits. This will assure that the desired bits will be accurately loaded into

the TDO_SM shifter and shifted out to the boundary scan chain. For instance, to shift a 3-bit (110) sequence the

partial long word should be written to the TDO_SM memory as shown in Figure 10 (only the least significant 16

bits are shown). A subsequent enable and load of the vector structure with the correct length will initialize the

shift operation and only the bits that are significant will be shifted out to the scan chain.

Figure 10. Writing a Partial Long Word to the TDO_SM Memory

Data is shifted from the scan chain into the TDI_SM shifter from MSB to LSB. Consequently, the valid

(meaningful) bits in a partial long word shifted into the TDI_SM shifter will reside in the upper significant bit

locations. For example, if a scan operation involves shifting and evaluating 69 bits returning to TDI_SM, the

TDI_SM memory will be loaded with two long words (i.e., two full long words plus a partial long word containing 5

meaningful bits). If the last 5 bits shifted back to the TDI_SM shifter are 11010, then upon completion of the shift

operation, the TDI_SM shifter will contain the following partial long word as shown in Figure 11 (only the most

significant 16 bits are shown), which will subsequently be loaded into the TDI_SM memory.

Following a read of a partial long word, the embedded test software must adjust the position of the valid bits read

from the TDI_SM shifter/buffer or the position of the expected data to assure that an accurate comparison is

made (and the non-meaningful bits are masked).

Figure 11. Reading a Partial Long Word from the TDI_SM Memory

TDO_SM IMPLEMENTATION

The behavior of the TDO_SM output depends on the macro type that is being processed and the SETUP register

bits 11 and 10, as shown in Table 12, regardless of the TAP tracker state. For shift macros, the TDO_SM output

also depends on the current macro structure's TMS_SM bit number as explained below.

Table 12. TDO_SM Output Behavior

SETUP[11:10]

TDO_SM

00

Hold Previous value

01 or 10

Default TDO value (Bit 6 of the SETUP register) (1)

11

High Impedance

(1)

Default TDO value (bit 6 of the SETUP register) may be set to a 0 when SETUP[11:10]=01 and to a 1 when SETUP[11:10]=10.

For BIST and STATE macros, the TDO_SM output behaves as shown in the above table.

For the shift macros, with or without capture, the TDO_SM output behaves as per the table only when the

corresponding TMS_SM output is not driven by the macro structure bit 7 or 8. On each falling edge of the

TCK_SM following the TCK_SM falling edge on which the TMS_SM changes state from bit 6 of the macro

structure to bit 7 of the macro structure, the serial test vector data fetched from the memory is presented on the

TDO_SM output. On the falling edge of the TCK_SM on which the final bit of the test vector is presented on the

TDO_SM output, the TMS_SM is presented with macro structure bit 8. On the subsequent TCK_SM falling

edges, and on the TCK_SM falling edges before the TMS_SM changes state from bit 6 to bit 7 of the macro

structure, the TDO_SM will behave as per the table above.

Copyright © 2002–2013, Texas Instruments Incorporated

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