SCANSTA101

SNLS057J – MAY 2002 – REVISED APRIL 2013

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PIN DESCRIPTIONS (continued)

Pin

No. Pins

I/O

Description

Name

TDI

1

I

Test Data In is the serial scan input to the SCANSTA101.

TMS

1

I

Test Mode Select. The Test Mode Select pin is a serial input used to

accept control logic to the test & debug interface.

TCK

1

I

Test Clock Input for 1149.1

TRST

1

I

Test Reset. This pin should be tied to ground by a 1K resistor to hold

the Test and Debug Interface in the Test-Logic-Reset state during

device power-up. This avoids invalid states when ramping supply

voltages.

TDI_SM

1

I

STA Master Test Data Input in the Serial Scan Interface

TDO_SM

1

O

STA Master Test Data Output in the Serial Scan Interface

TMS_SM

1

O

STA Master Test Mode Select in the Serial Scan Interface

TCK_SM

1

O

STA Master Test Clock in the Serial Scan Interface

TRST0_SM

1

O

STA Master Test Reset output in the Serial Scan Interface

TRST1_SM (1)

1

O

Redundant ScanMaster TRST. This signal is not available for the

packaged device.

TRIST_SM

1

O

The TRI-STATE notification pin exerts a high signal when TDO_SM is

at TRI-STATE

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

4

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