SCANSTA101

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SNLS057J – MAY 2002 – REVISED APRIL 2013

SCANSTA101 Low Voltage IEEE 1149.1 System Test Access (STA) Master

Check for Samples: SCANSTA101

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FEATURES

DESCRIPTION

The SCANSTA101 is designed to function as a test

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Compatible with IEEE Std. 1149.1 (JTAG) Test

master for an IEEE 1149.1 boundary scan test

Access Port and Boundary Scan Architecture

system. It is suitable for use in embedded IEEE

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Supported by Texas Instruments' SCAN Ease

1149.1 applications and as a component in a stand-

(SCAN Embedded Application Software

alone boundary scan tester.

Enabler) Software Rev 2.0

The SCANSTA101 is an enhanced version of, and a

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Uses Generic, Asynchronous Processor

replacement

for,

the

SCANPSC100.

The

Interface; Compatible with a Wide Range of

SCANSTA101 supports the IEEE 1149.1 Test Access

Processors and Processor Clock (PCLK)

Port (TAP) standard and the IEEE 1532 standard for

Frequencies

in-system configuration of programmable devices.

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16-Bit Data Interface (IP Scalable to 32-bit)

The SCANSTA101 improves test vector throughput

•

2k x 32 Bit Dual-Port Memory

and reduces software overhead in the system

processor. The SCANSTA101 presents a simple,

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Load-on-the-Fly (LotF) and Preloaded Vector

register-based interface to the system processor.

Operating Modes Supported

Texas Instruments provides C-language source code

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On-Board Sequencer Allows Multi-Vector

which can be included in the embedded system

Operations such as those Required to Load

software. The combination of the SCANSTA101 and

Data Into an FPGA

its support software comprises a simple API for

boundary scan operations.

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On-Board Compares Support Test Data In

(TDI) Validation Against Preloaded Expected

The interface from the SCANSTA101 to the system

Data

processor is implemented by reading and writing

registers, some of which map to locations in the

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32-Bit Linear Feedback Shift Register (LFSR)

SCANSTA101 memory. Hardware handshaking and

at the Test Data In (TDI) Port for Signature

interrupt lines are provided as part of the processor

Compression

interface.

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State, Shift, and BIST Macros Allow

The SCANSTA101 is available as a stand-alone

Predetermined Test Mode Select (TMS)

device packaged in a 49-pin NFBGA package. It is

Sequences to be Utilized

also available as an IP macro for synthesis in

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Operates at 3.3 V Supply Voltages with 5 V

programmable logic devices.

Tolerant I/O

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Outputs Support Power-Down TRI-STATE

Mode.

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Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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PRODUCTION DATA information is current as of publication date.

Copyright © 2002–2013, Texas Instruments Incorporated

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.