SCANSTA101SMSLASHNOPB datasheet(12/42 Pages) TI2

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SCANSTA101

SNLS057J – MAY 2002 – REVISED APRIL 2013

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All the control for this block is provided by the PIC and MRD with the 16/32-bit mode enable coming from the

Setup register.

EDGE DETECTOR

The PPI module can support either an asynchronous or synchronous processor interface. For an asynchronous

interface, the circuit initially synchronizes STB and CE to the system clock, SCK, by pipelining these two signals

through two flip-flop stages and then performing an edge detection on STB and CE. For a synchronous parallel

processor interface, this circuit just performs an edge detection. The outputs of this circuit, one clock wide pulses

indicating the detection of negative and positive edges, are used by the Processor Interface Controller (PIC)

state machine to start and to end a processor access.

PROCESSOR INTERFACE CONTROLLER

The Processor Interface Controller (PIC) monitors the incoming processor control signals and sets up the

appropriate internal control signals to move the data into memory or into an internal register on a write or to

move the data out of memory or out of an internal register on a read. The PIC edge detects the CE and the STB

to start the access. The PIC provides the control for the word to long word conversion in the WLWC by

controlling the three enables and the mux select (READ_MSW) to the capture registers. The PIC also controls

when the internal read/write enable is issued to the memory to complete the read/write operation. Timing for

MEMORY/REGISTER DECODER

The Memory/Register Decoder (MRD) contains all six index registers (Index, Vector Index, Header/Trailer Index,

Macro Index, Sequencer Index and ScanBridge Support Index) and four address registers (TDI_SM Address,

TDO_SM Address, Expected Address and Mask Address). On the PPI side, both index and address registers are

used to maintain pointers to their respective memory spaces. The Index register sets values in all four address

registers; i.e., writing to the Index register sets all of the address registers. The value written to each address

address registers except the Index register auto-increment with each access to the corresponding memory

space.

The MRD provides the address decode to generate all the control and status register enables for the CG and the

SIG. The MRD also provides the mux selects for the register or memory selection for the read capture operation

in the WLWC.

CONTROL GENERATOR

The Control Generator includes the seven control registers: the Start, Interrupt Control, Setup, Clock Divider,

TDI_SM LFSR Exponent, TDI_SM LFSR LSB Seed, and TDI_SM LFSR MSB Seed registers are included in this

block. The CG issues a strobe to the SSI when a write has been issued to the Start or Setup registers so the SSI

can react to the new control data. The strobe is derived from edge detecting the enables to the Start or Setup

registers. The "new" data to the SSI are the Use Sequencer bit and three Use Vector bits from the Start register,

and the TDO Default Value, TRST, ScanBridge Support Initiate/Release, three-bit Sync Bit Length, and two Test

Loop-back bits from the Setup register.

STATUS/INTERRUPT GENERATOR

The Status/Interrupt Generator comprises the four status registers plus the logic to generate the interrupts and to

clear the interrupts on a read. The registers are the Status, Interrupt Status, TDI_SM LFSR LSB Result and

TDI_SM LFSR MSB Result registers. The SIG receives the LFSR result and strobe signal SSI_LFSR_EN from

the SSI and captures the data in the LSB and MSB registers. The SIG receives the compare result bit value from

the SSI along with the compare result bit clear and the compare result bit load.

The SIG receives the 4 memory space flags from the FG along with their associated load and clear signals so

these bits may be constantly updated. The half-full, half-empty, full and empty flags are generated and updated

regardless of the states of their respective interrupt enables. The SIG also receives the four interrupt enables for

the flags. The SIG also receives the sequencer active and the three vector active signals from the SSI. These

are also updated regardless of the enable state.

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