DLP391TPFSB datasheet(33/46 Pages) TI2

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8 Power Supply Recommendations

The following power supplies are all required to operate the DMD:

• VSS

• VBIAS

• VDD

• VDDA

• VOFFSET

• VRESET

DMD power-up and power-down sequencing is strictly controlled by the DLP display controller.

CAUTION

For reliable operation of the DMD, the following power supply sequencing requirements must be

followed. Failure to adhere to any of the prescribed power-up and power-down requirements may

affect device reliability. See the DMD power supply sequencing requirements in Figure 8-1.

VBIAS, VDD, VDDA, VOFFSET, and VRESET power supplies must be coordinated during power-up and

power-down operations. Failure to meet any of the below requirements results in a significant

reduction in the DMD reliability and lifetime. Common ground VSS must also be connected.

Table 8-1. DMD Power Supply Sequence Requirements

SYMBOL

PARAMETER

DESCRIPTION

MIN

TYP

MAX UNIT

tDELAY1 (1)

Power up delay requirement

from VOFFSET settled at recommended operating

voltage to VBIAS and VRESET power up

tDELAY2 (1)

Power down delay requirement

Delay VDD must be held high from VOFFSET, VBIAS

and VRESET powering down.

VOFFSET

Supply voltage level

at beginning of power-up sequence delay

VBIAS

Supply voltage level

at end of power-up sequence delay

(1)

See Figure 8-1.

8.1 DMD Power Supply Power-Up Procedure

• During power-up, VDD and VDDA must always start and settle before VOFFSET plus Delay1, VBIAS, and VRESET

voltages are applied to the DMD.

• During power-up, it is a strict requirement that the voltage difference between VBIAS and VOFFSET must be

within the specified limit shown in the Section 5.4.

• During power-up, there is no requirement for the relative timing of VRESET with respect to VBIAS.

• Power supply slew rates during power-up are flexible, provided that the transient voltage levels follow the

requirements specified in Section 5.1, Section 5.4, and in Figure 8-1.

• During power-up, LVCMOS input pins must not be driven high until after VDD have settled at the operating

voltages listed in Recommended Operating Conditions.

8.2 DMD Power Supply Power-Down Procedure

• During power-down, VDD and VDDA must be supplied until after VBIAS, VRESET, and VOFFSET are discharged to

within the specified limit of ground.

• During power-down, it is a strict requirement that the voltage difference between VBIAS and VOFFSET must be

within the specified limit shown in Section 5.4.

• During power-down, there is no requirement for the relative timing of VRESET with respect to VBIAS.

• Power supply slew rates during power-down are flexible, provided that the transient voltage levels follow the

requirements specified in the Section 5.1, Section 5.4, and Figure 8-1.

• During power-down, LVCMOS input pins must be less than specified in the Section 5.4.

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DLP391TP

DLPS289A – JUNE 2025 – REVISED SEPTEMBER 2025

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