5.7 Switching Characteristics

Over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

tPD

Output propagation, clock to Q, rising edge of LS_CLK

input to LS_RDATA output. (1)

CL = 15pF

15

ns

Slew rate, LS_RDATA

0.3

V/ns

Output duty cycle distortion, LS_RDATA

40

60

%

(1)

Device electrical characteristics are over Section 5.4 unless otherwise noted.

5.8 Timing Requirements

Over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

NOM

MAX UNIT

LVCMOS

LPSDR

tr

Rise slew rate (2)

(20% to 80%) × VDD(6)

0.25

V/ns

tf

Fall slew rate (2)

(80% to 20%) × VDD(6)

0.25

V/ns

tr

Rise slew rate (1)

(30% to 80%) × VDD(6)

1

3

V/ns

tf

Fall slew rate (1)

(70% to 20%) × VDD(6)

1

3

V/ns

tW(H)

Pulse duration LS_CLK high

50% to 50% reference points(5)

4.2

ns

tW(L)

Pulse duration LS_CLK low

50% to 50% reference points(5)

4.2

ns

tsu

Setup time

LS_WDATA valid before LS_CLK(5)

1.5

ns

th

Hold time

LS_WDATA valid after LS_CLK(5)

1.5

ns

SubLVDS

tr

Rise slew rate

20% to 80% reference points(7)

0.7

1

V/ns

tf

Fall slew rate

80% to 20% reference points(7)

0.7

1

V/ns

tW(H)

Pulse duration DCLK high

50% to 50% reference points(8)

0.7

ns

tW(L)

Pulse duration DCLK low

50% to 50% reference points(8)

0.7

ns

tWINDOW

Window time (1) (3)

Setup time + Hold time(5)

0.25

ns

tsu

Setup time

HS_DATA valid before HS_CLK(8)

0.17

ns

th

Hold time

HS_DATA valid after HS_CLK(8)

0.17

ns

tPOWER

Power-up receiver(4)

200

ns

(1)

The specification is for the DMD_DEN_ARSTZ pin. Refer to the LPSDR input rise and fall slew rate in Figure 5-4.

(2)

The specification is for the LS_CLK and LS_WDATA pins. Refer to the LPSDR input rise and fall slew rate in Figure 5-4.

(3)

Window time derating example: 0.5V/ns slew rate increases the window time by 0.7ns, from 3ns to 3.7ns. See Figure 5-6.

(4)

The specification is for the SubLVDS receiver time only and does not take into account commanding and latency after commanding.

(5)

See Figure 5-3.

(6)

See Figure 5-4.

(7)

See Figure 5-5.

(8)

See Figure 5-7.

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DLP391TP

DLPS289A – JUNE 2025 – REVISED SEPTEMBER 2025

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