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LMKDB1104FS Scheda tecnica(PDF) 30 Page - Texas Instruments

Il numero della parte LMKDB1104FS
Spiegazioni elettronici  LMKDB11xx PCIe Gen 1 to Gen 7 Ultra Low Jitter LP-HCSL Clock Buffer Family
PDF  95 Pages
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Produttore elettronici  TI2 [Texas Instruments]
Homepage  https://www.ti.com
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LMKDB1104FS Scheda tecnica(HTML) 30 Page - Texas Instruments

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HCSL
CLKIN_P
CLKIN_N
Figure 8-3. HCSL Input Interface (PCIe Standard)
LVDS
CLKIN_P
CLKIN_N
Figure 8-4. LVDS Input Interface
AC Coupled
CLKIN_P
CLKIN_N
Bias
Figure 8-5. External AC-Coupled Input
HCSL – Rx Terminated
GND
CLKIN_P
CLKIN_N
Figure 8-6. Receiver Internal Terminations
8.3.1.3.1 Internal Termination for Clock Inputs
There is an option to enable 50Ω internal termination for differential clock input. For LP-HCSL input, disable
the internal termination. For HCSL input, enable internal termination if external termination is not provided. The
internal termination is disabled by default.
8.3.1.3.2 AC-Coupled or DC-Coupled Clock Inputs
Input clocks can be either AC coupled or DC coupled. If the inputs are DC coupled, the input signal
swing levels must match those in Specifications under the CLOCK INPUT REQUIREMENTS. Also, register
RX_EN_AC_INPUT must be set to 0 for DC-coupled inputs or set to 1 for AC-coupled inputs. Refer to the
Register Map for more information about RX_EN_AC_INPUT.
8.3.2 Flexible Power Sequence
8.3.2.1 PWRDN# Assertion and Deassertion
In the recommended power down sequence, PWRDN# is asserted while input clocks are valid. Make sure to
hold the PWRDN# pin at low level for two consecutive rising edges of the input clock cycle. As a result, all
clock outputs are muted to low/low (OUTx_P = Low, OUTx_N = Low) without a glitch. Following any other
sequence brings the device to an undefined mode and can cause glitches or invalid outputs - for example, if
PWRGD/PWRDN# is pulled low after the input clock is removed, the device enters a glitch state, where the
output gets stuck low (but only if the PWRGD/PWRDN# pin is not moved back from low to high before the
CLKIN signal is turned back on). If PWRGD/PWRDN# is pulled back to high before the CLKIN signal returns,
there are no issues.
8.3.2.2 OE# Assertion and Deassertion
OE# pins can be asserted and deasserted at anytime, whether:
LMKDB1102, LMKDB1104, LMKDB1104FS
LMKDB1108, LMKDB1108FS, LMKDB1120, LMKDB1120FS
SNAS855E – NOVEMBER 2023 – REVISED AUGUST 2025
www.ti.com
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Product Folder Links: LMKDB1102 LMKDB1104 LMKDB1104FS LMKDB1108 LMKDB1108FS LMKDB1120 LMKDB1120FS



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