LMKDB1104FS datasheet(72/95 Pages) TI2

Il numero della parte	LMKDB1104FS

Spiegazioni elettronici	LMKDB11xx PCIe Gen 1 to Gen 7 Ultra Low Jitter LP-HCSL Clock Buffer Family

PDF	95 Pages

Scroll/Zoom	100%

Produttore elettronici	TI2 [Texas Instruments]

Homepage	https://www.ti.com

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72 / 95 page

10.4 Layout

10.4.1 Layout Guidelines

Use a low-inductance ground connection between the device DAP and the PCB.

Match PCB trace impedance with device output impedance (85Ω or 100Ω differential impedance). Eliminate

stubs and reduce discontinuity on the transmission lines.

10.4.2 Layout Example

Figure 10-6. LMKDB1120 and LMKDB1120FS

Layout Example - Top Layer

Figure 10-7. LMKDB1120 and LMKDB1120FS

Layout Example - Bottom Layer

Figure 10-8. LMKDB1108 and LMKDB1108FS

Layout Example - Top Layer

Figure 10-9. LMKDB1108 and LMKDB1108FS

Layout Example - Bottom Layer

Figure 10-10. LMKDB1104 and LMKDB1104FS

Layout Example - Top Layer

Figure 10-11. LMKDB1104 and LMKDB1104FS

Layout Example - Bottom Layer

LMKDB1102, LMKDB1104, LMKDB1104FS

LMKDB1108, LMKDB1108FS, LMKDB1120, LMKDB1120FS

SNAS855E – NOVEMBER 2023 – REVISED AUGUST 2025

www.ti.com

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Product Folder Links: LMKDB1102 LMKDB1104 LMKDB1104FS LMKDB1108 LMKDB1108FS LMKDB1120 LMKDB1120FS

LMKDB1104FS Scheda tecnica(PDF) 72 Page - Texas Instruments