LMKDB1104FS datasheet(12/95 Pages) TI2

12 / 95 page

Table 5-3. LMKDB1104 and LMKDB1104FS Pin Functions (continued)

TYPE(1)

DESCRIPTION

NAME(2) (3)

NO.

VDDCLK

10, 15, 18, 25

Output power supply

Thermal Pad (GND)

Pad

Device Ground, Thermal pad.

LOGIC CONTROLS / STATUS

vOE0#/SHFT_LD#

Active low input to control CLK0 or SBI active low shift register load pin. SBI_EN pin

controls function of this pin. Internal pulldown resistor. OE mode: 0 = Active output, 1 =

Inactive output.

Side-Band Mode: SBI latch register input.

vOE1#/SBI_IN

Active low input to control CLK1 or SBI data input pin. SBI_EN pin controls function of this

pin. Internal pulldown resistor. OE mode: 0 = Active output, 1 = Inactive output.

Side-Band Mode: SBI data input.

vOE2#/SBI_CLK

Active low input to control CLK2 or SBI clock input pin. SBI_EN pin controls function of this

pin. Internal pulldown resistor. OE mode: 0 = Active output, 1 = Inactive output.

Side-Band Mode: SBI clock input.

vOE3#/SBI_OUT

I or O

Active low input to control CLK3 or SBI data output pin. Internal pulldown resistor. SBI_EN

pin controls function of this pin.

OE mode:0 = Active output, 1 = Inactive output.

SBI Mode: SBI shift register data output.

vPWRGD/PWRDN#

Power Good/Power Down Active Low. Multifunctional input pin. Internal pulldown resistor.

On the first low-to-high transition, functions as Power Good pin which starts up the device

On the subsequent low/high transitions, functions as Power Down Active Low pin which

controls the device to enter or exit power-down mode.

Low = power-down mode

High = normal operation mode

vSBI_EN

SBI Enable. Internal pulldown resistor. Do not change the state of this pin after power-up.

Low at power-up = SBI interface disabled. Pin 20, 32, 48 and 55 function as OE pins.

High at power-up = SBI interface enabled. Pin 20, 32, 48 and 55 function as SBI interface

pins. SMBus and other OE pins remain functional.

^vSADR1_tri

SMBus Address 3-level input pin. Internal pullup and pulldown resistors.

^vSADR0_tri

SMBus Address 3-level input pin. Internal pullup and pulldown resistors.

^SLEWRATE_SEL

LP-HCSL differential clock output slew rate select pin. Internal pullup resistor.

Low = Slow slew rate.

High = Fast slew rate.

LOS#

Loss of Input Clock Signal Active Low/No Connect. Open drain. Requires external pullup

resistor.

Low = Invalid input clock.

High = Valid input clock.

SMB_DATA

I/O

SMBus Data. Requires external pullup resistor. No connect if unused.

SMB_CLK

SMBus Clock. Requires external pullup resistor. No connect if unused.

No connect.

(1)

I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power, NC = No Connect

(2)

Pins with a "^" prefix have an internal pullup resistor. Pins with a "v" prefix have an internal pulldown resistor. Pins with a "^v" have an

internal pullup resistor and an internal pulldown resistor so that mid level is selected when the pin is left floating.

(3)

The "#" symbol indicates active low.

LMKDB1102, LMKDB1104, LMKDB1104FS

LMKDB1108, LMKDB1108FS, LMKDB1120, LMKDB1120FS

SNAS855E – NOVEMBER 2023 – REVISED AUGUST 2025

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