RC19302A00AGNT#BD0 datasheet(47/62 Pages) RENESAS

47 / 62 page

R31DS0210EU0106 Rev.1.06

Page 47

May 11, 2026

RC193xx Datasheet

Figure 18. Direct-Coupled Double-Terminated HCSL

The RC193xx CLK outputs can directly drive AC-coupling capacitors without any source-termination components.

The differential input will require an input-dependent bias network. This network may or may not be internal to the

receiver. Refer to the receiver specification for detailed requirements. AC-coupling is used to connect the

RC193xx to other logic families such as LVDS, LVPECL, or CML. See AN-891 for examples.

Figure 19. AC-Coupled Differential Input with Bias Network

Table 33 contains values for the items in the above figures.

5.3.2

Internal CLK Source Termination Disabled (ZOUT_SEL_tri = M)

ZOUT_SEL_tri = M disables the internal source termination making the differential ZO = 34ohms. This setting is

used with receiver terminated loads to provide a higher CLK amplitude to the load than can be obtained with a

double terminated configuration. The minimum single-ended amplitude in this configuration targets ~500mV. See

Table 21 for detailed specifications. This setting is intended for ZDIF =100 ohm systems.

Figure 20. Direct-Coupled Receiver-Terminated HCSL

Figure 21. Alternate Direct-Coupled Receiver-Terminated Input

Table 33. Parameters for

Internal CLK Source Termination Enabled

ZOUT_SEL_tri

ZO (ohms)

ZDIF (ohms)

RP (ohms)

CAC (uF)

ZDIF /2

0.1

100

ZDIF /2

0.1

RC193xx

HCSL

Input

ZDIF

RC193xx

Differential

Input

CAC

ZDIF

Differential

Input

ZDIF

RC193xx

Differential

Input

RC193xx

ZDIF

RC19302A00AGNT#BD0 Scheda tecnica(PDF) 47 Page - Renesas Technology Corp

RC19302A00AGNT#BD0 Scheda tecnica(HTML) 47 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62

Scheda tecnica Scarica

Link URL