MPC5606S datasheet(7/136 Pages) FREESCALE

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MPC5606S Microcontroller Data Sheet, Rev. 6

Freescale Semiconductor

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Real Time Counter (RTC) with multiple clock sources:

— 128 kHz slow internal RC oscillator or 16 MHz fast internal RC oscillator supporting autonomous wakeup with

1 ms resolution with maximum timeout of 2 seconds

— 32 KHz slow external crystal oscillator, supporting wakeup with 1 s resolution and maximum timeout of one hour

— 4–16 MHz fast external crystal oscillator

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System timers:

— 4-channel 32-bit System Timer Module (STM)—included in processor platform

— 4-channel 32-bit Periodic Interrupt Timer (PIT) module

— Software Watchdog Timer (SWT)

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System Integration Unit (SIU) module to manage resets, external interrupts, GPIO and pad control

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System Status and Configuration Module (SSCM) to provide information for identification of the device, last boot

mode, or debug status and provides an entry point for the censorship password mechanism

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Clock Generation Module (MC_CGM) to generate system clock sources and provide a unified register interface,

enabling access to all clock sources

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Clock Monitor Unit (CMU) to monitor the integrity of the main crystal oscillator and the PLL and act as a frequency

meter, measuring the frequency of one clock source and comparing it to a reference clock

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Mode Entry Module (MC_ME) to control the device power mode, i.e., RUN, HALT, STOP, or STANDBY, control

mode transition sequences, and manage the power control, voltage regulator, clock generation and clock management

modules

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Reset Generation Module (MC_RGM) to manage reset assertion and release to the device at initial power-up

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Nexus development interface (NDI) per IEEE-ISTO 5001-2003 Class Two Plus standard

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Device/board boundary-scan testing supported per Joint Test Action Group (JTAG) of IEEE (IEEE 1149.1)

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On-chip voltage regulator controller for regulating the 3.3 or 5 V supply voltage down to 1.2 V for core logic (requires

external ballast transistor)

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The MPC5606S microcontrollers are offered in the following packages:

— 144 LQFP, 0.5 mm pitch, 20 mm

 20 mm outline

— 176 LQFP, 0.5 mm pitch, 24 mm

 24 mm outline

— 208 MAPBGA, 1.0 mm pitch, 17 mm

 17 mm outline (not a production package; available in limited quantities

for tool development only)

1.6

Details

1.6.1

Low-power operation

MPC5606S devices are designed for optimized low-power operation and dynamic power management of the core processor and

peripherals. Power management features include software-controlled clock gating of peripherals and multiple power domains

to minimize leakage in low-power modes.

There are two static low-power modes, STANDBY and STOP, and two dynamic power modes—RUN and HALT. Both low

power modes use clock gating to halt the clock for all or part of the device. The STANDBY mode also uses power gating to

automatically turn off the power supply to parts of the device to minimize leakage.

STANDBY mode turns off the power to the majority of the chip to offer the lowest power consumption mode. The contents of

the cores, on-chip peripheral registers and potentially some of the volatile memory are lost. STANDBY mode is configurable

to make certain features available with the disadvantage that these consume additional current:

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It is possible to retain the contents of the full RAM or only 8 KB.

1. See the device comparison table or orderable parts summary for package offerings for each device in the family.

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