MPC5606S datasheet(17/136 Pages) FREESCALE

17 / 136 page

MPC5606S Microcontroller Data Sheet, Rev. 6

Freescale Semiconductor

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Up to 16 single-ended inputs channels

— All channels configured to have alternate function as general purpose input/output pins

–

10-bit ± 3 counts accuracy (TUE)

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External multiplexer support to increase up to 23 channels

— Automatic 1 × 8 multiplexer control

— External multiplexer connected to a dedicated input channel

— Shared register between the 8 external channels

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Result register available for every non-multiplexed channel

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Configurable Left or Right aligned result format

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Supports for one-shot, scan and injection conversion modes

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Injection mode status bit implemented on adjacent 16-bit register for each result

— Supports Access to Result and injection status with single 32-bit read

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Independently enabling of function for channels:

—Offset Refresh

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Conversion Triggering support

— Internal conversion triggering from periodic interrupt timer (PIT)

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4 configurable analog comparator channels offering range comparison with triggered alarm

— Greater than

— Less than

— Out of range

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All unused analog inputs can be used as general purpose input and output pins

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Power Down mode

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Optional support for DMA transfer of results

1.6.16

Deserial Serial Peripheral Interface (DSPI)

The deserial serial peripheral interface (DSPI) modules provide a synchronous serial interface for communication between the

MPC5606S MCU and external devices.

The DSPI features the following:

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Up to two DSPI modules

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Full duplex, synchronous transfers

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Master or slave operation

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Programmable master bit rates

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Programmable clock polarity and phase

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End-of-transmission interrupt flag

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Programmable transfer baud rate

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Programmable data frames from 4 to 16 bits

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Up to 6 chip select lines available, depending on package and pin multiplexing, enable 64 external devices to be

selected using external muxing from a single DSPI

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8 clock and transfer attributes registers

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Chip select strobe available as alternate function on one of the chip select pins for deglitching

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FIFOs for buffering up to 4 transfers on the transmit and receive side

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General purpose I/O functionality on pins when not used for SPI

•

Queueing operation possible through use of eDMA

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