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UCS1003-2 Scheda tecnica(PDF) 35 Page - Microchip Technology

Il numero della parte UCS1003-2
Spiegazioni elettronici  USB Port Power Controller with Charger Emulation
PDF  138 Pages
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Produttore elettronici  MICROCHIP [Microchip Technology]
Homepage  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

UCS1003-2 Scheda tecnica(HTML) 35 Page - Microchip Technology

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 2014-2015 Microchip Technology Inc.
DS20005346B-page 35
UCS1003-1/2/3
5.1.1
OFF STATE OPERATION
The device is in the OFF state if VDD is less than
VDD_TH. When the UCS1003-1/2/3 devices are in the
OFF state, it does nothing and all circuitry is disabled.
In the case of UCS1003-1, the digital register values
are not stored and the device will not respond to
SMBus commands.
5.1.2
SLEEP STATE OPERATION
When the UCS1003-1/2/3 devices are in the Sleep
state, the device is in its lowest power state. The high-
speed switch, bypass switch and the port power switch
are disabled. The Attach and Removal Detection
feature is disabled. VBUS will be near ground potential.
The ALERT# pin is not asserted. If asserted prior to
entering the Sleep state, the ALERT# pin will be
released. The A_DET# pin is released. In the case of
UCS1003-1, SMBus activity is limited to single byte
read or write.
The first data byte read from the UCS1003-1, when in
the Sleep state, will wake the device; however, the data
to be read will return all ‘0’s and should be considered
invalid. This is a “dummy” read byte meant to wake the
UCS1003-1. Subsequent read or write bytes will be
accepted normally. After the dummy read, the
UCS1003-1 will be in a higher power state (see
Figure 5-6). The device will return to Sleep after the last
communication or if no further communication has
occurred.
Figure 5-5 shows the timing diagrams for waking the
UCS1003-1/2/3 family via external pins. Figure 5-6
shows the timing for waking the UCS1003-1 device via
SMBus.
FIGURE 5-5:
Wake Timing via External Pins.
FIGURE 5-6:
Wake via SMBus Read with S0 = 0.
M1 or M2
Port Power Switch Closed
(Active state)
tPIN_WAKE
Wake with M1 or M2 to Active State Data Pass-Through Mode
(PWR_EN enabled, S0 = 0, EM_EN = 0, VS > VS_UVLO)
S0
Bypass Switch Closed
(Detect state)
tPIN_WAKE
Wake with S0
(VS > VS_UVLO, M1 & M2 & EM_EN not all ‘0’s and not set to data pass-through)
0101_1110
A
invalid
data
NP
SMBus Read
A
0001_0000
0101_1110
A
valid data
NP
0001_0000
S
S
tIDLE_SLEEP
Sleep
Sleep
Dummy Read Returns Invalid Data and Places Device in
Temporary Active State
Read Returns Valid Data
0101_1111
A
S
0101_1111
A
S
A
Power State
Temporary Active State
(not all functionality available)
tSMB_WAKE



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