UCS1003-2 datasheet(37/138 Pages) MICROCHIP

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DS20005346B-page 37

UCS1003-1/2/3

When the UCS1003-1/2/3 enters the Error state, the

port power switch, VBUS bypass switch and the high-

speed switch are turned off, and the ALERT# pin is

asserted (by default). They will remain off while in this

power state. The UCS1003-1/2/3 will leave this state as

determined by the Fault handling selection (see

Section 7.5 “Fault Handling Mechanism”

When using the latch Fault handler and the user has re-

activated the device by clearing the ERR bit (for

UCS1003-1 only, see Section 10.3 “Status Registers”)

or toggling the PWR_EN control, the UCS1003-1/2/3 will

check that all of the error conditions have been removed.

If using the auto-recovery Fault handler, after the tCYCLE

time period, the UCS1003-1/2/3 will check that all of the

error conditions have been removed.

If all of the error conditions have been removed, the

UCS1003-1/2/3 will return to the Active state or Detect

state, as applicable. Returning to the Active state will

cause the UCS1003-1/2/3 to restart the selected mode

(see Section 9.2 “Active Mode Selection”).

If the device is in the Error state and a Removal

Detection event occurs, it will check the error

conditions and then return to the power state defined

by the PWR_EN, M1, M2, EM_EN and S0 controls.

5.2

Supply Voltages

5.2.1

VDD SUPPLY VOLTAGE

The UCS1003-1/2/3 family requires 4.5V to 5.5V to be

present on the VDD pin for core device functionality.

Core device functionality consists of maintaining

Attach Detection.

5.2.2

VS SOURCE VOLTAGE

VS can be a separate supply and can be greater than

VDD to accommodate high-current applications in

which current path resistances result in unacceptable

voltage drops that may prevent optimal charging of

some portable devices.

5.2.3

BACK-VOLTAGE DETECTION

Whenever the following conditions are true, the port

power switch will be disabled, the VBUS bypass switch

will be disabled, the high-speed data switch will be dis-

abled and a back-voltage event will be flagged. This will

cause the UCS1003-1/2/3 to enter the Error power

state (see Section 5.1.5 “Error State Operation”).

•The VBUS voltage exceeds the VS voltage by

VBV_TH and the port power switch is closed. The

port power switch will be opened immediately. If

the condition lasts for longer than tMASK, then the

UCS1003-1/2/3 will enter the Error state. Other-

wise, the port power switch will be turned on as

soon as the condition is removed.

•The VBUS voltage exceeds the VDD voltage by

VBV_TH and the VBUS bypass switch is closed.

The bypass switch will be opened immediately. If

the condition lasts for longer than tMASK, then the

UCS1003-1/2/3 will enter the Error state. Other-

wise, the bypass switch will be turned on as soon

as the condition is removed.

5.2.4

BACKDRIVE CURRENT

PROTECTION

If a self-powered portable device is attached, it may

drive the VBUS port to its power supply voltage level;

however, the UCS1003-1/2/3 family is designed such

that leakage current from the VBUS pins to the VDD or

VS pins shall not exceed IBD_1 (if the VDD voltage is

zero), or IBD_2 (if the VDD voltage exceeds VDD_TH).

5.2.5

UNDERVOLTAGE LOCKOUT ON VS

The UCS1003-1/2/3 family requires a minimum voltage

(VS_UVLO) be present on the VS pin for the Active power

state.

5.2.6

OVERVOLTAGE DETECTION AND

LOCKOUT ON VS

The UCS1003-1/2/3 port power switch will be disabled

if the voltage on the VS pin exceeds a voltage (VS_OV)

for longer than the specified time (tMASK). This will

cause the device to enter the Error state.

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