UCS1003-3 datasheet(127/138 Pages) MICROCHIP

127 / 138 page

 2014-2015 Microchip Technology Inc.

DS20005346B-page 127

UCS1003-1/2/3

11.2.1.3

SMBus Data Bytes

All SMBus data bytes are sent Most Significant bit

(MSb) first and composed of eight bits of information.

11.2.1.4

SMBus ACK and NACK Bits

The SMBus client will Acknowledge all data bytes that

it receives. This is done by the client device pulling the

SMBus data line low after the eighth bit of each byte

that is transmitted. This applies to both the write byte

and block write protocols.

By holding the SMBus data line high after the eighth data

bit has been sent, the host will NACK (not Acknowledge)

the last data byte to be received from the client. For the

block read protocol, the host will ACK each data byte

that it receives, except the last data byte.

11.2.1.5

SMBus Stop Bit

The SMBus Stop bit is defined as a transition of the

SMBus data line from a logic ‘0’ state to a logic ‘1’ state

while the SMBus clock line is in a logic ‘1’ state. When

the UCS1003-1 detects an SMBus Stop bit, and it has

been communicating with the SMBus protocol, it will

reset its client interface and prepare to receive further

communications.

11.2.1.6

SMBus Time-out and Idle Reset

The UCS1003-1 includes an SMBus time-out feature.

If the clock is held at logic ‘0’ for tTIMEOUT, the device

can time-out and reset the SMBus interface. The

SMBus interface can also reset if both the clock and

data lines are held at a logic ‘1’ for tIDLE_RESET.

Communication is restored with a Start condition. This

functionality defaults to disabled and can be enabled by

clearing the DIS_TO bit in the Emulation Configuration

11.2.2

SMBUS AND I2C COMPATIBILITY

The major differences between SMBus and I2C devices

are highlighted in this section. For more information, refer

to the SMBus 2.0 and I2C specifications.

• UCS1003-1 supports I2C Fast mode at 400 kHz.

This covers the SMBus maximum time of 100 kHz.

• Minimum frequency for SMBus communications

is 10 kHz.

• The SMBus client protocol will reset if the clock is

held at a logic ‘0’ for longer than 30 ms. This time-

out functionality is disabled by default in the

UCS1003-1 and can be enabled by clearing the

DIS_TO bit. I2C does not have a time-out.

• Except when operating in Sleep mode, the

SMBus client protocol will reset if both the clock

and data lines are held at a logic ‘1’ for longer

than 200 µs (Idle condition). This function is dis-

abled by default in the UCS1003-1 device and

can be enabled by clearing the DIS_TO bit. I2C

does not have an Idle condition.

•I2C devices do not support the Alert Response

Address functionality (which is optional for SMBus).

•I2C devices support block read and write

differently. I2C protocol allows for an unlimited

number of bytes to be sent in either direction. The

SMBus protocol requires that an additional data

byte, indicating the number of bytes to read/write,

is transmitted. The UCS1003-1 supports I2C

formatting only.

TABLE 11-2:

SEL PIN DECODE

Resistor (±5%)

PWR_EN Polarity

SMBus Address

GND

Active-Low

1010_111

(R/W)

10 k

 pull-down

Active-Low

1010_110

(R/W)

12 k

 pull-down

Active-Low

1010_101

(R/W)

15 k

 pull-down

Active-Low

1010_100

(R/W)

18 k

 pull-down

Active-Low

0110_000

(R/W)

22 k

 pull-down

Active-Low

0110_001

(R/W)

27 k

 pull-down

Active-Low

0110_010

(R/W)

33 k

 pull-down

Active-Low

0110_011

(R/W)

47 k

 pull-down

Active-High

0110_011

(R/W)

56 k

 pull-down

Active-High

0110_010

(R/W)

68 k

 pull-down

Active-High

0110_001

(R/W)

82 k

 pull-down

Active-High

0110_000

(R/W)

100 k

 pull-down

Active-High

1010_100

(R/W)

120 k

 pull-down

Active-High

1010_101

(R/W)

150 k

 pull-down

Active-High

1010_110

(R/W)

VDD (If a pull-up resistor is used,

its value must not exceed 100 k

)

Active-High

1010_111

(R/W)

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