T25S16AFEPR datasheet(55/74 Pages) HMSEMI

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7.4.2 Software Reset (99h)

The Reset (99h) command immediately following a Reset Enable (66h) command, initiates the software

reset process. Any command other than Reset (99h) following the Reset Enable (66h) command, will clear the

reset enable condition and prevent a later Reset (99h) command from being recognized.

7.5 ID and Security Commands

7.5.1 Deep Power-down (DP) (B9h)

Although the standby current during normal operation is relatively low, standby current can be further

reduced with the Power-down instruction. The lower power consumption makes the Power- down instruction

especially useful for battery powered applications (See ICC1 and ICC2 in AC Characteristics). The instruction

is initiated by driving the CS# pin low and shifting the instruction code “B9h” as shown in Figure 7.27.

The CS# pin must be driven high after the eighth bit has been latched. If this is not done, the Power-

down instruction will not be executed. After CS# is driven high, the power-down state will enter within the time

duration of tDP (See AC Characteristics). While in the power-down state only the Release from Power-down /

Device ID instruction, which restores the device to normal operation, will be recognized. All other instructions

are ignored. This includes the Read Status Register instruction, which is always available during normal

operation. Ignoring all but one instruction makes the Power Down state a useful condition for securing

maximum write protection. The device always powers-up in the normal operation with the standby current of

ICC1.

Figure 7.27 Deep Power-down Instruction(SPI and QPI Mode)

7.5.2 Release Power-down / Device ID (ABh)

The Release from Power-down / Device ID instruction is a multi-purpose instruction. It can be used to

release the device from the power-down state, obtain the devices electronic identification (ID) number or both.

To release the device from the power-down state, the instruction is issued by driving the CS# pin low,

shifting the instruction code “ABh” and driving CS# high as shown in Figure 7.28. After the time duration of

tRES1 (See AC Characteristics) the device will resume normal operation and other instructions will be accepted.

The CS# pin must remain high during the tRES1 time duration.

When used only to obtain the Device ID during the non-power-down state, the instruction is initiated by

driving the CS# pin low and shifting the instruction code “ABh” followed by 3-dummy bytes. The Device ID bits

will then be shifted out on the falling edge of CLK with most significant bit (MSB) first as shown in Figure 7.29.

The Device ID value for the

HM25Q128A is listed in Manufacturer and Device Identification table. The Device

ID can be read continuously. The instruction is completed by driving CS# high.

When used to release the device from the power-down state and obtain the Device ID, the instruction is

the same as previously described, and shown in Figure 7.29, except that after CS# is driven high it must

remain high for a time duration of tRES2 (See AC Characteristics). After this time duration the device will

resume normal operation and other instructions will be accepted. If the Release from Power-down / Device ID

instruction is issued within Erase, Program or Write cycle (when BUSY equals 1), the instruction is ignored

and will not have any effects on the current cycle.

HM25Q128A

T25S16AFEPR Scheda tecnica(PDF) 55 Page - Shenzhen Huazhimei Semiconductor Co., Ltd